SNVS440B May 2007 – March 2016 LP5520
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| V (SW, FB, ROUT, GOUT, BOUT) | –0.3 | 22 | V | |
| VDDA, VDDD, VDDIO, VLDO | –0.3 | 6 | V | |
| Voltage on logic pins | –0.3 V to VDDIO | 0.3 V with 6 V maximum | V | |
| Continuous power dissipation(4) | Internally limited | |||
| Junction temperature, TJ-MAX | 125 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±200 | |||
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| V (SW, FB, ROUT, GOUT, BOUT) | 0 | 21 | V | |
| VDDA,DDD | 2.9 | 5.5 | V | |
| VDDIO | 1.65 | VDDA | V | |
| Recommended load current (ROUT, GOUT, BOUT) per driver | 0 | 60 | mA | |
| Junction temperature, TJ | –30 | 125 | °C | |
| Ambient temperature, TA(2) | –30 | 85 | °C | |
| THERMAL METRIC(1) | LP5520 | UNIT | |
|---|---|---|---|
| YZR (DSBGA) | |||
| 25 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 58.2 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 0.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 7.9 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 7.9 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IVDD | Standby supply current (VDDA + VDDD) |
NSTBY = L, VDDIO ≥ 1.65 V | 1.7 | 7 | µA | |
| NSTBY = L , VDDIO = 0 V | 1 | |||||
| No-boost supply current (VDDA + VDDD) |
NSTBY = H, EN_BOOST = L |
0.9 | mA | |||
| No-load supply current (VDDA + VDDD) |
NSTBY = H, EN_BOOST = H AUTOLOAD = L |
1.4 | ||||
| IVDDIO | VDDIO standby supply current | NSTBY = L | 1 | µA | ||
| VLDO | Internal LDO output voltage | VIN ≥ 2.9 V, TJ = 25°C | 2.77 | 2.80 | 2.84 | V |
| ILDO | Internal LDO output current | Current to external load | 1 | mA | ||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ILEAKAGE | ROUT, GOUT, BOUT pin leakage current | 0.1 | 1 | µA | ||
| IMAX | Maximum sink current | Outputs ROUT, GOUT, BOUT control = 255 (FFH) | 60 | mA | ||
| IR | Current accuracy of ROUT, GOUT, and BOUT | Output current set to 20 mA | 19 | 20 | 21 | mA |
| –5% | 5% | |||||
| Output current set to 60 mA | 54 | 60 | 66 | mA | ||
| –10% | 10% | |||||
| IMATCH | Matching(1) | Between ROUT, GOUT, BOUT at 20 mA current | ±0.2% | ±2% | ||
| tPWM | PWM cycle time | Accuracy proportional to internal clock frequency | 820 | µs | ||
| ƒRGB | RGB switching frequency | <pwm_fast> = 0 | 1.22 | kHz | ||
| <pwm_fast> = 1 | 19.52 | |||||
| VSAT | Saturation voltage(2) | I(LED) = 60 mA | 550 | mV | ||
| ƒMAX | External PWM maximum frequency | I(LED) = 60 mA, TJ = 25°C | 1 | MHz | ||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| LOGIC INPUTS SS, SI/A0, SCK/SCL, IFSEL, NRST, PWMR, PWMG, PWMB and BRC | ||||||
| VIL | Input low level | 0.2 × VDDIO | V | |||
| VIH | Input high level | 0.8 × VDDIO | V | |||
| II | Logic input current | −1 | 1 | µA | ||
| ƒSCK/SLC | Clock frequency | I2C mode | 0.4 | MHz | ||
| SPI mode, VDDIO > 1.8 V | 13 | |||||
| SPI mode, 1.65 V < VDDIO < 1.8 V | 5 | |||||
| LOGIC INPUT NRST | ||||||
| VIL | Input low level | 05 | V | |||
| VIH | Input high level | 1.2 | V | |||
| II | Logic input current | –1 | 1 | µA | ||
| tNRST | Reset pulse width | 10 | µs | |||
| LOGIC OUTPUT SO | ||||||
| VOL | Output low level | ISO = 3 mA VDDIO > 1.8 V |
0.3 | 0.5 | V | |
| ISO = 2 mA 1.65 V < VDDIO < 1.8 V |
0.3 | 0.5 | V | |||
| VOH | Output high level | ISO = –3 mA VDDIO > 1.8 V |
VDDIO − 0.5 | VDDIO − 0.3 | V | |
| ISO = –2 mA 1.65 V < VDDIO < 1.8 V |
VDDIO − 0.5 | VDDIO − 0.3 | V | |||
| IL | Output leakage current | VSO = 2.8 V | 1 | µA | ||
| LOGIC OUTPUT SDA | ||||||
| VOL | Output low level | ISDA = 3 mA | 0.3 | 0.5 | V | |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ILOAD | Maximum continuous load current | 2.9V = VIN, VOUT = 20 V TJ = 25°C |
70 | mA | ||
| VOUT | Output voltage accuracy (FB pin) | 2.9 ≤ VIN ≤ 5.5 V, VOUT = 20 V TJ = 25°C |
–1.7% | 1.7% | ||
| 2.9 ≤ VIN ≤ 5.5 V, VOUT = 20 V | –5% | 5% | ||||
| RDSON | Switch ON resistance | ISW = 0.5 A | 0.3 | Ω | ||
| ƒPWM | Frequency accuracy | TJ = 25°C | −6% | ±3% | 6% | |
| –9% | 9% | |||||
| tPULSE | Switch pulse minimum width | no load | 50 | ns | ||
| tSTARTUP | Start-up time | 20 | ms | |||
| IMAX | SW pin current limit | 1100 | mA | |||
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| 1 | Hold time (repeated) START condition | 0.6 | µs | |
| 2 | Clock low time | 1.3 | µs | |
| 3 | Clock high time | 600 | ns | |
| 4 | Setup time for a repeated START condition | 600 | ns | |
| 5 | Data hold time (output direction, delay generated by LP5520) | 300 | 900 | ns |
| 5 | Data hold time (input direction, delay generated by Master) | 0 | 900 | ns |
| 6 | Data setup time | 100 | ns | |
| 7 | Rise time of SDA and SCL | 20 + 0.1Cb | 300 | ns |
| 8 | Fall time of SDA and SCL | 15 + 0.1Cb | 300 | ns |
| 9 | Setup time for STOP condition | 600 | ns | |
| 10 | Bus free time between a STOP and a START condition | 1.3 | µs | |
| Cb | Capacitive load for each bus line | 10 | 200 | pF |
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| 1 | Cycle time | 70 | ns | |
| 2 | Enable lead time | 35 | ns | |
| 3 | Enable lag time | 35 | ns | |
| 4 | Clock low time | 35 | ns | |
| 5 | Clock high time | 35 | ns | |
| 6 | Data setup time | 0 | ns | |
| 7 | Data hold time | 25 | ns | |
| 8 | Data access time | 30 | ns | |
| 9 | Disable time | 20 | ns | |
| 10 | Data valid | 40 | ns | |
| 11 | Data hold time | 0 | ns | |
Figure 1. I2C Timing Diagram
Figure 2. SPI Timing Diagram
Figure 3. VSAT vs ILED
Figure 4. VSAT vs ILED
Figure 5. Boost Maximum Output Voltage vs Current
Figure 7. Auto-Load Effect on Input Current, No Load
Figure 6. Battery Current vs Voltage
Figure 8. Adaptive Output Voltage Operation