SNVSCE3B May   2023  – November 2023 LP5866T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
        1. 7.3.2.1 Global 3-Bits Maximum Current (MC) Setting
        2. 7.3.2.2 3 Groups of 7-Bits Color Current (CC) Setting
        3. 7.3.2.3 Individual 8-bit Dot Current (DC) Setting
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 Individual 8-Bit / 16-Bit PWM for Each LED Dot
        2. 7.3.3.2 Programmable Groups of 8-Bit PWM Dimming
        3. 7.3.3.3 8-Bit PWM for Global Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
        1. 7.3.7.1 LED Open Detection
        2. 7.3.7.2 LED Short Detection
        3. 7.3.7.3 Thermal Shutdown
        4. 7.3.7.4 UVLO (Under Voltage Lock Out)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Interface Selection
      2. 7.5.2 I2C Interface
        1. 7.5.2.1 I2C Data Transactions
        2. 7.5.2.2 I2C Data Format
        3. 7.5.2.3 Multiple Devices Connection
      3. 7.5.3 Programming
        1. 7.5.3.1 SPI Data Transactions
        2. 7.5.3.2 SPI Data Format
        3. 7.5.3.3 Multiple Devices Connection
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD Input Supply Recommendations
      2. 8.3.2 VLED Input Supply Recommendations
      3. 8.3.3 VIO Input Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Data Refresh Mode

The LP5866T supports three data refresh modes: Mode 1, Mode 2, and Mode 3, by configuring 'Data_Ref_Mode' in Dev_initial register.

Mode 1: 8-bit PWM data without VSYNC command. Data is sent out for display instantly after received. With Mode1, users can refresh the corresponding dots' data only instead of updating the whole SRAM. It is called ‘on demand data refresh’, which can save the total data volume effectively. As shown in Figure 7-7, the red LED dots can be refreshed after sending the corresponding data while the others kept the same with last frame.

GUID-03C679BE-AAF7-4D4B-A3EA-E7A707C92348-low.svgFigure 7-7 On Demand Data Refresh - Mode 1

Mode 2: 8-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Mode 3: 16-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Frame control is implemented in Mode 2 and Mode 3. Instead of refreshing the output instantly after data is received (Mode 1), the device holds the data and refreshes the whole frame data by a fixed frame rate, fVSYNC. Usually, 24Hz, 50Hz, 60Hz, 120Hz or even higher frame rate is selected to achieve vivid animation effects. Whole SRAM Data Refresh is shown in Figure 7-8, a new frame is updated after receiving the VSYNC command.

GUID-D7A710EB-F383-41DE-95E1-2C857A257974-low.svgFigure 7-8 Whole SRAM Data Refresh

Comparing with Mode 1, Mode 2 and Mode 3 provide a better synchronization when multiple LP5866T devices used together. A high-level pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame. Figure 7-9 shows the VSYNC connections and Figure 7-10 shows the timing requirements.

GUID-1D39C6A9-265A-43AC-A392-5693E277C780-low.svg Figure 7-9 Multiple Devices Sync
GUID-B5514E01-2583-4F3B-A967-CC69EEFE240B-low.svg Figure 7-10 VSYNC Timing
Table 8-4 is the summary of the 3 data refresh modes.
Table 7-4 Data Refresh Mode
MODE TYPEPWM RESOLUTIONPWM OUTPUTEXTERNAL VSYNC
Mode 18 BitsData update instantlyNo
Mode 28 BitsData update by frameYes
Mode 316 Bits