SNVSAW2B April   2017  – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 DC-DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnostics and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnostics (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
          1. Table 10. OTP_REV Register Field Descriptions
        2. 7.6.1.2  BUCK0_CTRL1
          1. Table 11. BUCK0_CTRL1 Register Field Descriptions
        3. 7.6.1.3  BUCK1_CTRL1
          1. Table 12. BUCK1_CTRL1 Register Field Descriptions
        4. 7.6.1.4  BUCK2_CTRL1
          1. Table 13. BUCK2_CTRL1 Register Field Descriptions
        5. 7.6.1.5  BUCK3_CTRL1
          1. Table 14. BUCK3_CTRL1 Register Field Descriptions
        6. 7.6.1.6  BUCK0_VOUT
          1. Table 15. BUCK0_VOUT Register Field Descriptions
        7. 7.6.1.7  BUCK0_FLOOR_VOUT
          1. Table 16. BUCK0_FLOOR_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 17. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  BUCK1_FLOOR_VOUT
          1. Table 18. BUCK1_FLOOR_VOUT Register Field Descriptions
        10. 7.6.1.10 BUCK2_VOUT
          1. Table 19. BUCK2_VOUT Register Field Descriptions
        11. 7.6.1.11 BUCK2_FLOOR_VOUT
          1. Table 20. BUCK2_FLOOR_VOUT Register Field Descriptions
        12. 7.6.1.12 BUCK3_VOUT
          1. Table 21. BUCK3_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK3_FLOOR_VOUT
          1. Table 22. BUCK3_FLOOR_VOUT Register Field Descriptions
        14. 7.6.1.14 BUCK0_DELAY
          1. Table 23. BUCK0_DELAY Register Field Descriptions
        15. 7.6.1.15 BUCK1_DELAY
          1. Table 24. BUCK1_DELAY Register Field Descriptions
        16. 7.6.1.16 BUCK2_DELAY
          1. Table 25. BUCK2_DELAY Register Field Descriptions
        17. 7.6.1.17 BUCK3_DELAY
          1. Table 26. BUCK3_DELAY Register Field Descriptions
        18. 7.6.1.18 GPIO2_DELAY
          1. Table 27. GPIO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPIO3_DELAY
          1. Table 28. GPIO3_DELAY Register Field Descriptions
        20. 7.6.1.20 RESET
          1. Table 29. RESET Register Field Descriptions
        21. 7.6.1.21 CONFIG
          1. Table 30. CONFIG Register Field Descriptions
        22. 7.6.1.22 INT_TOP1
          1. Table 31. INT_TOP1 Register Field Descriptions
        23. 7.6.1.23 INT_TOP2
          1. Table 32. INT_TOP2 Register Field Descriptions
        24. 7.6.1.24 INT_BUCK_0_1
          1. Table 33. INT_BUCK_0_1 Register Field Descriptions
        25. 7.6.1.25 INT_BUCK_2_3
          1. Table 34. INT_BUCK_2_3 Register Field Descriptions
        26. 7.6.1.26 TOP_STAT
          1. Table 35. TOP_STAT Register Field Descriptions
        27. 7.6.1.27 BUCK_0_1_STAT
          1. Table 36. BUCK_0_1_STAT Register Field Descriptions
        28. 7.6.1.28 BUCK_2_3_STAT
          1. Table 37. BUCK_2_3_STAT Register Field Descriptions
        29. 7.6.1.29 TOP_MASK1
          1. Table 38. TOP_MASK1 Register Field Descriptions
        30. 7.6.1.30 TOP_MASK2
          1. Table 39. TOP_MASK2 Register Field Descriptions
        31. 7.6.1.31 BUCK_0_1_MASK
          1. Table 40. BUCK_0_1_MASK Register Field Descriptions
        32. 7.6.1.32 BUCK_2_3_MASK
          1. Table 41. BUCK_2_3_MASK Register Field Descriptions
        33. 7.6.1.33 SEL_I_LOAD
          1. Table 42. SEL_I_LOAD Register Field Descriptions
        34. 7.6.1.34 I_LOAD_2
          1. Table 43. I_LOAD_2 Register Field Descriptions
        35. 7.6.1.35 I_LOAD_1
          1. Table 44. I_LOAD_1 Register Field Descriptions
        36. 7.6.1.36 PGOOD_CTRL1
          1. Table 45. PGOOD_CTRL1 Register Field Descriptions
        37. 7.6.1.37 PGOOD_CTRL2
          1. Table 46. PGOOD_CTRL2 Register Field Descriptions
        38. 7.6.1.38 PGOOD_FLT
          1. Table 47. PGOOD_FLT Register Field Descriptions
        39. 7.6.1.39 PLL_CTRL
          1. Table 48. PLL_CTRL Register Field Descriptions
        40. 7.6.1.40 PIN_FUNCTION
          1. Table 49. PIN_FUNCTION Register Field Descriptions
        41. 7.6.1.41 GPIO_CONFIG
          1. Table 50. GPIO_CONFIG Register Field Descriptions
        42. 7.6.1.42 GPIO_IN
          1. Table 51. GPIO_IN Register Field Descriptions
        43. 7.6.1.43 GPIO_OUT
          1. Table 52. GPIO_OUT Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Current Limit vs. Maximum Output Current
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNF|26
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT Output filtering Capacitance, local Capacitance per phase 10 22 µF
CPOL Point-of-Load (POL) capacitance Optional POL capacitance per phase 22 µF
COUT-TOTAL Output capacitance, total (local and POL) Total output capacitance, 1-phase output 100 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ
L Inductor Inductance of the inductor 0.47 µH
–30% 30%
DCRL Inductor DCR 25 mΩ
BUCK REGULATOR
VVIN_Bx Input voltage range 2.8 3.7 5.5 V
VVOUT_Bx Output voltage Programmable voltage range, 2.8 V ≤ VVIN_Bx ≤ 4 V 0.6 3.36 V
Programmable voltage range, 2.8 V ≤ VVIN_Bx ≤ 5.5 V 1.0 3.36
Step size, 0.6 V ≤ VOUT < 0.73 V 10 mV
Step size, 0.73 V ≤ VOUT < 1.4 V 5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT Output current, LP87524B/J Buck0, Buck1 1.5(3) A
Buck2: VIN ≥ 3 V 4(3)
Buck2: 2.8 V ≤ VIN < 3 V 3(3)
Buck3 2.5(3)
IOUT Output current, LP87524P Buck0, Buck2 3(3) A
Buck1 1.5(3)
Buck3 2.5(3)
Input and output voltage difference Minimum voltage between VIN_x and VOUT to fulfill the electrical characteristics 0.5 V
VVOUT_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature VOUT < 1 V, PWM mode –20 20 mV
VOUT ≥ 1 V, PWM mode –2% 2%
VOUT < 1 V, PFM mode –20 40 mV
VOUT ≥ 1 V, PFM mode –2% 2% + 20 mV
Ripple voltage PWM mode, ESRC < 2 mΩ, L = 0.47 µH 4 mVp-p
PFM mode, L = 0.47 µH 14
DCLNR DC line regulation IOUT = IOUT(max) 0.1 %/V
DCLDR DC load regulation in PWM mode VOUT = 1 V, IOUT from 0 to IOUT(max) 0.8%
TLDSR Transient load step response IOUT = 0 A to 2 A, TR = TF = 10 µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF –3% 3% mV
IOUT = 0.1 A to 2 A, TR = TF = 1 µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF ±40
TLNSR Transient line response VVIN_Bx stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±5 mV
ILIM FWD Forward current limit (peak for every switching cycle), LP87524B/J Buck0, Buck1: VVIN_Bx ≥ 3 V 2.3 2.7 3.0 A
Buck0, Buck1: 2.8 V ≤ VVIN_Bx < 3 V 2.0 2.7 3.0
Buck2: VVIN_Bx ≥ 3 V 4.7 5.4 6.0
Buck2: 2.8 V ≤ VVIN_Bx < 3 V 4.0 5.4 6.0
Buck3: VVIN_Bx ≥ 3 V 4.2 4.8 5.4
Buck3: 2.8 V ≤ VVIN_Bx < 3 V 3.6 4.8 5.4
ILIM FWD Forward current limit (peak for every switching cycle), LP87524P Buck0, Buck2: VVIN_Bx ≥ 3 V 3.8 4.3 4.8 A
Buck0, Buck2: 2.8 V ≤ VVIN_Bx < 3 V 3.2 4.3 4.8
Buck1: VVIN_Bx ≥ 3 V 2.3 2.7 3.0
Buck1: 2.8 V ≤ VVIN_Bx < 3 V 2.0 2.7 3.0
Buck3: VVIN_Bx ≥ 3 V 4.2 4.8 5.4
Buck3: 2.8 V ≤ VVIN_Bx < 3 V 3.6 4.8 5.4
ILIM NEG Negative current limit / phase (peak for every switching cycle) 1.6 2 2.4 A
RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 29 65 mΩ
RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 17 35 mΩ
fSW Switching frequency, PWM mode VOUT > 0.8 3.6 4 4.4 MHz
0.6 < VOUT ≤ 0.8 2.7 3 3.3
VOUT = 0.6 1.8 2 2.2
Start-up time (soft start) From ENx to VOUT = 0.35 V (slew-rate control begins), COUT_TOTAL = 44 µF / phase 200 µs
Output voltage slew-rate(4) 3.23 3.8 4.4 mV/µs
IPFM-PWM PFM-to-PWM - current threshold(5) 600 mA
IPWM-PFM PWM-to-PFM - current threshold(5) 200 mA
Output pulldown resistance Regulator disabled 160 230 300 Ω
Output voltage monitoring for PGOOD pin Overvoltage monitoring (compared to DC output voltage level, VVOUT_DC) 39 50 64 mV
Undervoltage monitoring (compared to DC output voltage level, VVOUT_DC) –53 –40 –29
Debounce time during regulator enable PGOOD_SET_DELAY = 0 4 10 µs
Debounce time during regulator enable PGOOD_SET_DELAY = 1 10 11 13 ms
Deglitch time during operation and after voltage change 4 10 µs
Powergood threshold for interrupt BUCKx_PG_INT, difference from final voltage Rising ramp voltage, enable or voltage change –20 –14 –8 mV
Falling ramp voltage, voltage change 8 14 20
Powergood threshold for status bit BUCKx_PG_STAT During operation, status signal is forced to '0' during voltage change –20 –14 –8 mV
EXTERNAL CLOCK AND PLL
External input clock Nominal frequency 1 24 MHz
Nominal frequency step size 1
Required accuracy from nominal frequency –30% 10%
External clock detection Delay for missing clock detection 1.8 µs
Delay and debounce for clock detection 20
Clock change delay (internal to external) Delay from valid clock detection to use of external clock 600 µs
PLL output clock jitter Cycle to cycle 300 ps, p-p
PROTECTION FUNCTIONS
Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1 127 137 147
Hysteresis 20
Thermal shutdown Temperature rising 140 150 160 °C
Hysteresis 20
VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V
Voltage falling 5.45 5.73 5.96
Hysteresis 40 mV
VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V
Voltage falling 2.5 2.6 2.7
LOAD CURRENT MEASUREMENT
Current measurement range Output current for maximum code  20.47 A
Resolution LSB 20 mA
Measurement accuracy IOUT > 1 A <10%
Measurement time PFM mode (automatically changing to PWM mode for the measurement) 45 µs
PWM mode 4
CURRENT CONSUMPTION
Shutdown current consumption From VANA and VIN_Bx pins: NRST = 0 V, VANA = VIN_Bx = 3.7 V 1.4 µA
Standby current consumption, regulators disabled From VANA and VIN_Bx pins: NRST = 1.8 V, VANA = VIN_Bx = 3.7 V 6.7
Active current consumption in PFM mode, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled From VANA and VIN_Bx pins: NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching 57 µA
Active current consumption during PWM operation, per phase 19 mA
PLL and clock detector current consumption Additional current consumption when internal RC oscillator, clock detector and PLL are enabled 2 mA
DIGITAL INPUT SIGNALS NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
VIL Input low level 0.4 V
VIH Input high level 1.2
VHYS Hysteresis of Schmitt Trigger inputs 10 77 200 mV
ENx pulldown resistance ENx_PD = 1 500 kΩ
NRST pulldown resistance Always present 650 1150 1700
DIGITAL OUTPUT SIGNALS nINT
VOL Output low level ISOURCE = 2 mA 0.4 V
RP External pullup resistor To VIO supply 10 kΩ
DIGITAL OUTPUT SIGNALS SDA
VOL Output low level ISOURCE = 10 mA 0.4 V
DIGITAL OUTPUT SIGNALS PGOOD, GPIO1, GPIO2, GPIO3
VOL Output low level ISOURCE = 2 mA 0.4 V
VOH Output high level, configured to push-pull ISINK = 2 mA VVANA – 0.4 VVANA V
VPU Supply voltage for external pull-up resistor, configured to open-drain VVANA V
RPU External pullup resistor, configured to open-drain 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range (except NRST) −1 1 µA
(1) All voltage values are with respect to network ground.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.
(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level.