SNVSBP2 February   2020 LP8758-E3

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
        1. 7.1.1.1 Operating Modes
        2. 7.1.1.2 Programmability
        3. 7.1.1.3 Features
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overview
        1. 7.3.1.1 Transition between PWM and PFM Modes
        2. 7.3.1.2 Buck Converter Load Current Measurement
        3. 7.3.1.3 Spread-Spectrum Mode
      2. 7.3.2 Power-Up
      3. 7.3.3 Regulator Control
        1. 7.3.3.1 Enabling and Disabling
        2. 7.3.3.2 Changing Output Voltage
      4. 7.3.4 Device Reset Scenarios
      5. 7.3.5 Diagnosis and Protection Features
        1. 7.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 7.3.5.1.1 Output Current Limit
          2. 7.3.5.1.2 Thermal Warning
        2. 7.3.5.2 Protection (Regulator Disable)
          1. 7.3.5.2.1 Short-Circuit and Overload Protection
          2. 7.3.5.2.2 Thermal Shutdown
        3. 7.3.5.3 Fault (Power Down)
          1. 7.3.5.3.1 Undervoltage Lockout
      6. 7.3.6 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
        2. 7.6.1.2  BUCK0_CTRL1
        3. 7.6.1.3  BUCK0_CTRL2
        4. 7.6.1.4  BUCK1_CTRL1
        5. 7.6.1.5  BUCK1_CTRL2
        6. 7.6.1.6  BUCK2_CTRL1
        7. 7.6.1.7  BUCK2_CTRL2
        8. 7.6.1.8  BUCK3_CTRL1
        9. 7.6.1.9  BUCK3_CTRL2
        10. 7.6.1.10 BUCK0_VOUT
        11. 7.6.1.11 BUCK0_FLOOR_VOUT
        12. 7.6.1.12 BUCK1_VOUT
        13. 7.6.1.13 BUCK1_FLOOR_VOUT
        14. 7.6.1.14 BUCK2_VOUT
        15. 7.6.1.15 BUCK2_FLOOR_VOUT
        16. 7.6.1.16 BUCK3_VOUT
        17. 7.6.1.17 BUCK3_FLOOR_VOUT
        18. 7.6.1.18 BUCK0_DELAY
        19. 7.6.1.19 BUCK1_DELAY
        20. 7.6.1.20 BUCK2_DELAY
        21. 7.6.1.21 BUCK3_DELAY
        22. 7.6.1.22 RESET
        23. 7.6.1.23 CONFIG
        24. 7.6.1.24 INT_TOP
        25. 7.6.1.25 INT_BUCK_0_1
        26. 7.6.1.26 INT_BUCK_2_3
        27. 7.6.1.27 TOP_STAT
        28. 7.6.1.28 BUCK_0_1_STAT
        29. 7.6.1.29 BUCK_2_3_STAT
        30. 7.6.1.30 TOP_MASK
        31. 7.6.1.31 BUCK_0_1_MASK
        32. 7.6.1.32 BUCK_2_3_MASK
        33. 7.6.1.33 SEL_I_LOAD
        34. 7.6.1.34 I_LOAD_2
        35. 7.6.1.35 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Input Capacitor Selection
          3. 8.2.2.1.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Register Descriptions

The LP8758-E3 is controlled by a set of registers through the serial interface port. The device registers, their addresses and their abbreviations are listed in Table 5. A more detailed description is given in sections OTP_REV to I_LOAD_1.

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.

Table 5. Summary of LP8758-E3 Control Registers

Addr Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0
0x01 OTP_REV R OTP_ID[7:0]
0x02 BUCK0_
CTRL1		 R/W EN_BUCK0 EN_PIN_
CTRL0		 EN_PIN_
SELECT0		 EN_ROOF
_FLOOR0		 EN_RDIS0 Reserved BUCK0_
FPWM		 Reserved
0x03 BUCK0_
CTRL2		 R/W Reserved ILIM0[2:0] SLEW_RATE0[2:0]
0x04 BUCK1_
CTRL1		 R/W EN_BUCK1 EN_PIN_
CTRL1		 EN_PIN_
SELECT1		 EN_ROOF
_FLOOR1		 EN_RDIS1 Reserved BUCK1_
FPWM		 Reserved
0x05 BUCK1_
CTRL2		 R/W Reserved ILIM1[2:0] SLEW_RATE1[2:0]
0x06 BUCK2_
CTRL1		 R/W EN_BUCK2 EN_PIN_
CTRL2		 EN_PIN_
SELECT2		 EN_ROOF
_FLOOR2		 EN_RDIS2 Reserved BUCK2_
FPWM		 Reserved
0x07 BUCK2_
CTRL2		 R/W Reserved ILIM2[2:0] SLEW_RATE2[2:0]
0x08 BUCK3_
CTRL1		 R/W EN_BUCK3 EN_PIN_
CTRL3		 EN_PIN_
SELECT3		 EN_ROOF
_FLOOR3		 EN_RDIS3 Reserved BUCK3_
FPWM		 Reserved
0x09 BUCK3_
CTRL2		 R/W Reserved ILIM3[2:0] SLEW_RATE3[2:0]
0x0A BUCK0_
VOUT		 R/W BUCK0_VSET[7:0]
0x0B BUCK0_
FLOOR_
VOUT		 R/W BUCK0_FLOOR_VSET[7:0]
0x0C BUCK1_
VOUT		 R/W BUCK1_VSET[7:0]
0x0D BUCK1_
FLOOR_
VOUT		 R/W BUCK1_FLOOR_VSET[7:0]
0x0E BUCK2_
VOUT		 R/W BUCK2_VSET[7:0]
0x0F BUCK2_
FLOOR_
VOUT		 R/W BUCK2_FLOOR_VSET[7:0]
0x10 BUCK3_
VOUT		 R/W BUCK3_VSET[7:0]
0x11 BUCK3_
FLOOR_
VOUT		 R/W BUCK3_FLOOR_VSET[7:0]
0x12 BUCK0_
DELAY		 R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0]
0x13 BUCK1_
DELAY		 R/W BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0]
0x14 BUCK2_
DELAY		 R/W BUCK2_SHUTDOWN_DELAY[3:0] BUCK2_STARTUP_DELAY[3:0]
0x15 BUCK3_
DELAY		 R/W BUCK3_SHUTDOWN_DELAY[3:0] BUCK3_STARTUP_DELAY[3:0]
0x16 RESET R/W Reserved SW_
RESET
0x17 CONFIG R/W Reserved TDIE
_WARN
_LEVEL		 EN2_PD EN1_PD EN_
SPREAD
_SPEC
0x18 INT_TOP R/W INT_
BUCK3		 INT_
BUCK2		 INT_
BUCK1		 INT_
BUCK0		 TDIE_SD TDIE_
WARN		 RESET_
REG		 I_LOAD_
READY
0x19 INT_BUCK_0_1 R/W Reserved BUCK1_
PG_INT		 BUCK1_
SC_INT		 BUCK1_
ILIM_INT		 Reserved BUCK0_
PG_INT		 BUCK0_
SC_INT		 BUCK0_
ILIM_INT
0x1A INT_BUCK_2_3 R/W Reserved BUCK3_
PG_INT		 BUCK3_
SC_INT		 BUCK3_
ILIM_INT		 Reserved BUCK2_
PG_INT		 BUCK2_
SC_INT		 BUCK2_
ILIM_INT
0x1B TOP_
STAT		 R Reserved TDIE_SD
_STAT		 TDIE_
WARN_
STAT		 Reserved
0x1C BUCK_0_1_STAT R BUCK1_
STAT		 BUCK1_
PG_STAT		 Reserved BUCK1_
ILIM_
STAT		 BUCK0_
STAT		 BUCK0_
PG_STAT		 Reserved BUCK0_
ILIM_
STAT
0x1D BUCK_2_3_STAT R BUCK3_
STAT		 BUCK3_
PG_STAT		 Reserved BUCK3_
ILIM_STAT		 BUCK2_
STAT		 BUCK2_
PG_STAT		 Reserved BUCK2_
ILIM_STAT
0x1E TOP_
MASK		 R/W Reserved TDIE_WARN_MASK RESET_
REG_MASK		 I_LOAD_
READY_
MASK
0x1F BUCK_0_1_MASK R/W Reserved BUCK1_
PG_MASK		 Reserved BUCK1_
ILIM_
MASK		 Reserved BUCK0_
PG_MASK		 Reserved BUCK0_
ILIM_
MASK
0x20 BUCK_2_3_MASK R/W Reserved BUCK3_
PG_MASK		 Reserved BUCK3_
ILIM_
MASK		 Reserved BUCK2_
PG_MASK		 Reserved BUCK2_
ILIM_
MASK
0x21 SEL_I_
LOAD		 R/W Reserved LOAD_CURRENT_
BUCK_SELECT[1:0]
0x22 I_LOAD_2 R/W Reserved BUCK_LOAD_CURRENT[9:8]
0x23 I_LOAD_1 R/W BUCK_LOAD_CURRENT[7:0]