SDLS972B April   2023  – April 2024 LSF0102

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  LSF0102 AC Performance (Translating Down) Switching Characteristics , VCCB = 3.3V
    7. 5.7  LSF0102 AC Performance (Translating Down) Switching Characteristics, VCCB = 2.5V
    8. 5.8  LSF0102 AC Performance (Translating Up) Switching Characteristics, VCCB = 3.3V
    9. 5.9  LSF0102 AC Performance (Translating Up) Switching Characteristics, VCCB = 2.5V
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Auto Bidirectional Voltage Translation
      2. 7.3.2 Output Enable
    4. 7.4 Device Functional Modes
      1. 7.4.1 Up and Down Translation
        1. 7.4.1.1 Up Translation
        2. 7.4.1.2 Down Translation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Open-Drain Interface (I2C, PMBus, SMBus, and GPIO)
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
          2. 8.2.1.1.2 Bias Circuitry
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Bidirectional Translation
          2. 8.2.1.2.2 Pull-Up Resistor Sizing
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Mixed-Mode Voltage Translation
      3. 8.2.3 Single Supply Translation
      4. 8.2.4 Voltage Translation for Vref_B < Vref_A + 0.8V
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
  12. 11Revision History

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • DDF|8
  • YZT|8
  • DCT|8
  • DQE|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Output Enable

To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be pulled up to the HIGH side (VCCB) through a bias resistor (typically 200kΩ). To be in the high impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor. This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device.

GUID-20221006-SS0I-GKJG-5LHQ-6KP3NRBHJ4ZW-low.svg Figure 7-1 Enable Pin Tied to Vref_B Directly and to VCCB Through a Bias Resistor

The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video.

Table 7-1 Enable Pin Function Table
INPUT EN(1) PINData Port State
Tied directly to Vref_BAn = Bn
LHi-Z
(1) EN is controlled by Vref_B logic levels.