SLVSCP5H July   2014  – April 2021 LSF0204 , LSF0204D

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
    7. 7.7  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
    8. 7.8  Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
    9. 7.9  Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit AC Waveform for Outputs
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Support High Speed Translation, Greater than 100 MHz
      2. 9.3.2 Bidirectional Voltage Translation Without DIR Terminal
      3. 9.3.3 5-V Tolerance on IO Port and 125°C Support
      4. 9.3.4 Channel Specific Translation
      5. 9.3.5 Ioff, Partial Power Down Mode
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 I2C PMBus, SMBus, GPIO, Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Bidirectional Translation
            1. 10.2.1.2.1.1 Pull-Up Resistor Sizing
          2. 10.2.1.2.2 LS Family Bandwidth
        3. 10.2.1.3 Application Curve
      2. 10.2.2 MDIO Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Multiple Voltage Translation in Single Device, Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|14
  • YZP|12
  • RUT|12
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.2.1.2.2 LS Family Bandwidth

The maximum frequency of the LSF family is dependent on the application. The device may operate at speeds of >100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the on resistance and on capacitance of the device.

Figure 10-2 shows a bandwidth measurement of the LSF family using a two-port network analyzer.

GUID-62694FB9-1618-4F46-BE3C-585E26AEB6FC-low.gifFigure 10-2 3-dB Bandwidth

The 3-dB point of the LSF family is ≈600 MHz; however, this measurement is an analog type of measurement. For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock frequency of greater than 100 MHz may be achieved.

The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF family is being driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the LSF family on the sink side (1.8 V) to minimize signal degradation.

All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than fknee are insignificant in determining the shape of the signal.

To calculate the maximum practical frequency component, or the knee frequency (fknee), use the following equations:

Equation 2. fknee = 0.5/RT (10–80%)
Equation 3. fknee = 0.4/RT (20–80%)

For signals with rise time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the signal.

Some guidelines to follow that will help maximize the performance of the device:

  • Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
  • The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
  • To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.