Try to run the feedback trace as far from the noisy power or clocking traces as possible. In the case that the OSC pin is not being used, as in Figure 31, the FB trace can be ran on a lower layer under the OSC pin. When OSC is being utilized by a noisy clocking signal, it is recommended to run the FB trace on a lower layer through the Vref pin.
Keep the FB trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from EMI and other noise sources is the more critical of the two.
Keep the external capacitor traces short, specifically on the CAP+ and CAP- nodes that have the fastest rise and fall times.
Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.