SLLS708E January   2006  – December 2024 MAX3222E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2.     ESD Ratings
    3.     ESD Ratings - IEC Specifications
    4. 5.2 Recommended Operating Conditions
    5. 5.3 Thermal Information
    6. 5.4 Electrical Characteristics
    7. 5.5 Electrical Characteristics: Driver
    8. 5.6 Switching Characteristics: Driver
    9. 5.7 Electrical Characteristics: Receiver
    10. 5.8 Switching Characteristics: Receiver
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The MAX3222E consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15kV ESD protection pin to pin (serial-port connection pins, including GND).

The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3V to 5.5V supply. The device operates at typical data signaling rates up to 500kbit/s and a maximum of 30V/μs driver output slew rate.

The MAX3222E can be placed in the power-down mode by setting the power-down ( PWRDOWN) input low, which draws only 1μA from the power supply. When the device is powered down, the receivers remain active while the drivers are placed in the high-impedance state. Also, during power down, the onboard charge pump is disabled; V+ is lowered to VCC, and V– is raised toward GND. Receiver outputs also can be placed in the high-impedance state by setting enable ( EN) high.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
MAX3222E DB (SSOP, 20) 7.2mm x 7.8mm
DW (SOIC, 20) 12.8mm x 10.3mm
PW (TSSOP, 20) 6.5mm x 6.4mm
DGS (VSSOP, 20) 5.1mm x 4.9mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
MAX3222E Logic Diagram (Positive Logic)
Pin numbers are for the DB, DW, and PW packages.
Logic Diagram (Positive Logic)