3- to 5.5-V dual channel 500kbps RS-232 line driver/receiver with +/-15-kV IEC-ESD protection
Product details
Parameters
Package | Pins | Size
Features
- ESD Protection for RS-232 Bus Pins
- ±15-kV Human-Body Model (HBM)
- ±8-kV IEC61000-4-2, Contact Discharge
- ±15-kV IEC61000-4-2, Air-Gap Discharge
- Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards - Operates With 3-V to 5.5-V VCC Supply
- Operates up to 500 kbit/s
- Two Drivers and Two Receivers
- Low Standby Current . . . 1 µA Typ
- External Capacitors . . . 4 × 0.1 µF
- Accepts 5-V Logic Input With 3.3-V Supply
- Alternative High-Speed Pin-Compatible Device (1 Mbit/s) for SNx5C3222E
- APPLICATIONS
- Battery-Powered Systems
- PDAs
- Notebooks
- Laptops
- Palmtop PCs
- Hand-Held Equipment
Description
The MAX3222E consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND).
The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The device operates at typical data signaling rates up to 500 kbit/s and a maximum of 30-V/µs driver output slew rate.
The MAX3222E can be placed in the power-down mode by setting the power-down (PWRDOWN) input low, which draws only 1 µA from the power supply. When the device is powered down, the receivers remain active while the drivers are placed in the high-impedance state. Also, during power down, the onboard charge pump is disabled; V+ is lowered to VCC, and V is raised toward GND. Receiver outputs also can be placed in the high-impedance state by setting enable (EN) high.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | MAX3222E datasheet (Rev. A) | Sep. 29, 2009 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DW) | 20 | View options |
SSOP (DB) | 20 | View options |
TSSOP (PW) | 20 | View options |
Ordering & quality
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