SLLSFU1 December   2023 MCF8315C

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Under Voltage Protection
        7. 6.3.3.7 Buck Over Current Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog Mode Motor Control
        2. 6.3.8.2 PWM Mode Motor Control
        3. 6.3.8.3 I2C based Motor Control
        4. 6.3.8.4 Frequency Mode Motor Control
        5. 6.3.8.5 Speed Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Reference Profiles
          3. 6.3.8.5.3 Forward-Reverse Reference Profiles
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
      11. 6.3.11 Motor Start-up
        1. 6.3.11.1 Align
        2. 6.3.11.2 Double Align
        3. 6.3.11.3 Initial Position Detection (IPD)
          1. 6.3.11.3.1 IPD Operation
          2. 6.3.11.3.2 IPD Release Mode
          3. 6.3.11.3.3 IPD Advance Angle
        4. 6.3.11.4 Slow First Cycle Start-up
        5. 6.3.11.5 Open loop
        6. 6.3.11.6 Transition from Open to Closed Loop
      12. 6.3.12 Closed Loop Operation
        1. 6.3.12.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.12.2 Speed PI Control
        3. 6.3.12.3 Current PI Control
        4. 6.3.12.4 Torque Mode
        5. 6.3.12.5 Overmodulation
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Modulation Schemes
      19. 6.3.19 Dead Time Compensation
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Low-Side Braking
        3. 6.3.20.3 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG during open loop
        3. 6.3.21.3 FG during idle and fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  VM Supply Undervoltage Lockout
        2. 6.3.23.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.23.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.23.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.23.5  Overvoltage Protection (OVP)
        6. 6.3.23.6  Overcurrent Protection (OCP)
          1. 6.3.23.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.23.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.23.7  Buck Overcurrent Protection
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.23.9  Motor Lock (MTR_LCK)
          1. 6.3.23.9.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.9.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.9.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.9.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock Detection
          1. 6.3.23.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.23.11 Minimum VM (undervoltage) Protection
        12. 6.3.23.12 Maximum VM (overvoltage) Protection
        13. 6.3.23.13 MPET Faults
        14. 6.3.23.14 IPD Faults
        15. 6.3.23.15 Thermal Warning (OTW)
        16. 6.3.23.16 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC output (only in RRY package)
      3. 6.5.3 Oscillator Source
        1. 6.5.3.1 External Clock Source
      4. 6.5.4 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Thermal Considerations
      1. 9.2.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8.4 Algorithm_Control Registers

Table 6-58 lists the memory-mapped registers for the Algorithm_Control registers. All register offset addresses not listed in Table 6-58 should be considered as reserved locations and the register contents should not be modified.

Table 6-58 ALGORITHM_CONTROL Registers
OffsetAcronymRegister NameSection
EChALGO_DEBUG1Algorithm Control RegisterSection 6.8.4.1
EEhALGO_DEBUG2Algorithm Control RegisterSection 6.8.4.2
F0hCURRENT_PICurrent PI Controller usedSection 6.8.4.3
F2hSPEED_PISpeed PI controller usedSection 6.8.4.4
F4hDACDAC1 Control RegisterSection 6.8.4.5

Complex bit access types are encoded to fit into small table cells. Table 6-59 shows the codes that are used for access types in this section.

Table 6-59 Algorithm_Control Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.8.4.1 ALGO_DEBUG1 Register (Offset = ECh) [Reset = 00000000h]

ALGO_DEBUG1 is shown in Figure 6-87 and described in Table 6-60.

Return to the Summary Table.

Algorithm control register for debug

Figure 6-87 ALGO_DEBUG1 Register
3130292827262524
OVERRIDEDIGITAL_SPEED_CTRL
W-0hW-0h
2322212019181716
DIGITAL_SPEED_CTRL
W-0h
15141312111098
CLOSED_LOOP_DISFORCE_ALIGN_ENFORCE_SLOW_FIRST_CYCLE_ENFORCE_IPD_ENFORCE_ISD_ENFORCE_ALIGN_ANGLE_SRC_SELFORCE_IQ_REF_SPEED_LOOP_DIS
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
FORCE_IQ_REF_SPEED_LOOP_DIS
W-0h
Table 6-60 ALGO_DEBUG1 Register Field Descriptions
BitFieldTypeResetDescription
31OVERRIDEW0h Use to control the reference input mode. If OVERRIDE = 1b, speed command can be written by the user through I2C interface.
0h = Reference input based on SPEED_MODE
1h = Reference input based on DIGITAL_SPEED_CTRL
30-16DIGITAL_SPEED_CTRLW0h If OVERRIDE = 1b or SPEED_MODE = 10b, then reference input is from DIGITAL_SPEED_CTRL
15CLOSED_LOOP_DISW0h Use to disable closed loop
0h = Enable closed loop
1h = Disable closed loop, motor commutation in open loop
14FORCE_ALIGN_ENW0h Force align state
0h = Disable force align state, device comes out of align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN
1h = Enable force align state, device stays in align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN
13FORCE_SLOW_FIRST_CYCLE_ENW0h Force slow first cycle
0h = Disable force slow first cycle state, device comes out of slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE
1h = Enable force slow first cycle state, device stays in slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE
12FORCE_IPD_ENW0h Force IPD
0h = Disable force IPD state, device comes out of IPD state if MTR_STARTUP is selected as IPD
1h = Enable force IPD state, device stays in IPD state if MTR_STARTUP is selected as IPD
11FORCE_ISD_ENW0h Force ISD enable
0h = Disable force ISD state, device comes out of ISD state if ISD_EN is set
1h = Enable force ISD state, device stays in ISD state if ISD_EN is set
10FORCE_ALIGN_ANGLE_SRC_SELW0h Force align angle state source
0h = Force align angle defined by ALIGN_ANGLE
1h = Force align angle defined by FORCED_ALIGN_ANGLE
9-0FORCE_IQ_REF_SPEED_LOOP_DISW0h Sets IQ ref (% of BASE_CURRENT) when speed loop is disabled If SPEED_LOOP_DIS = 1b, then Iq_ref is control using IQ_REF_SPEED_LOOP_DIS iqRef = (FORCE_IQ_REF_SPEED_LOOP_DIS /500) * BASE_CURRENT if FORCE_IQ_REF_SPEED_LOOP_DIS < 500 (FORCE_IQ_REF_SPEED_LOOP_DIS - 1024)/500 * BASE_CURRENT if FORCE_IQ_REF_SPEED_LOOP_DIS > 512 Valid values are 0 to 500 and 512 to 1000

6.8.4.2 ALGO_DEBUG2 Register (Offset = EEh) [Reset = 00000000h]

ALGO_DEBUG2 is shown in Figure 6-88 and described in Table 6-61.

Return to the Summary Table.

Algorithm control register for debug

Figure 6-88 ALGO_DEBUG2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDCURRENT_LOOP_DISFORCE_VD_CURRENT_LOOP_DIS
R-0hR-0hR-0hW-0hW-0h
2322212019181716
FORCE_VD_CURRENT_LOOP_DIS
W-0h
15141312111098
FORCE_VQ_CURRENT_LOOP_DIS
W-0h
76543210
FORCE_VQ_CURRENT_LOOP_DISMPET_CMDMPET_RMPET_LMPET_KEMPET_MECHMPET_WRITE_SHADOW
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 6-61 ALGO_DEBUG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h Reserved
30-28RESERVEDR0h Reserved
27RESERVEDR0h Reserved
26CURRENT_LOOP_DISW0h Use to control the FORCE_VD_CURRENT_LOOP_DIS and FORCE_VQ_CURRENT_LOOP_DIS. If CURRENT_LOOP_DIS = '1', Current loop and speed loop is disabled
0h = Enable current loop
1h = Disable current loop
25-16FORCE_VD_CURRENT_LOOP_DISW0h Sets Vd when current and speed loops are disabled If CURRENT_LOOP_DIS = 1b, then Vd is control using FORCE_VD_CURRENT_LOOP_DIS mdRef = (FORCE_VD_CURRENT_LOOP_DIS /500) if FORCE_VD_CURRENT_LOOP_DIS < 500 (FORCE_VD_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VD_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000
15-6FORCE_VQ_CURRENT_LOOP_DISW0h Sets Vq when current and speed loops are disabled If CURRENT_LOOP_DIS = 1b, then Vq is control using FORCE_VQ_CURRENT_LOOP_DIS mqRef = (FORCE_VQ_CURRENT_LOOP_DIS /500) if FORCE_VQ_CURRENT_LOOP_DIS < 500 (FORCE_VQ_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VQ_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000
5MPET_CMDW0h Initiates motor parameter measurement routine when set to 1b
4MPET_RW0h Enables motor resistance measurement during motor parameter measurement routine
0h = Disables motor resistance measurement during motor parameter measurement routine
1h = Enable motor resistance measurement during motor parameter measurement routine
3MPET_LW0h Enables motor inductance measurement during motor parameter measurement routine
0h = Disables motor inductance measurement during motor parameter measurement routine
1h = Enable motor inductance measurement during motor parameter measurement routine
2MPET_KEW0h Enables motor BEMF constant measurement during motor parameter measurement routine
0h = Disables motor BEMF constant measurement during motor parameter measurement routine
1h = Enable motor BEMF constant measurement during motor parameter measurement routine
1MPET_MECHW0h Enables motor mechanical parameter measurement during motor parameter measurement routine
0h = Disables motor mechanical parameter measurement during motor parameter measurement routine
1h = Enable motor mechanical parameter measurement during motor parameter measurement routine
0MPET_WRITE_SHADOWW0h Write measured parameters to shadow register when set to 1b

6.8.4.3 CURRENT_PI Register (Offset = F0h) [Reset = 00000000h]

CURRENT_PI is shown in Figure 6-89 and described in Table 6-62.

Return to the Summary Table.

Current PI controller used

Figure 6-89 CURRENT_PI Register
313029282726252423222120191817161514131211109876543210
CURRENT_LOOP_KICURRENT_LOOP_KP
R-0hR-0h
Table 6-62 CURRENT_PI Register Field Descriptions
BitFieldTypeResetDescription
31-16CURRENT_LOOP_KIR0h 10-bit register for current loop Ki Same scaling as CURR_LOOP_KI
15-0CURRENT_LOOP_KPR0h 10-bit register for current loop Kp Same scaling as CURR_LOOP_KP

6.8.4.4 SPEED_PI Register (Offset = F2h) [Reset = 00000000h]

SPEED_PI is shown in Figure 6-90 and described in Table 6-63.

Return to the Summary Table.

Speed PI controller used

Figure 6-90 SPEED_PI Register
313029282726252423222120191817161514131211109876543210
SPEED_LOOP_KISPEED_LOOP_KP
R-0hR-0h
Table 6-63 SPEED_PI Register Field Descriptions
BitFieldTypeResetDescription
31-16SPEED_LOOP_KIR0h 10-bit register for speed loop Ki Same Scaling as SPD_LOOP_KI
15-0SPEED_LOOP_KPR0h 10-bit register for speed loop Kp Same Scaling as SPD_LOOP_KP

6.8.4.5 DAC Register (Offset = F4h) [Reset = 00110000h]

DAC is shown in Figure 6-91 and described in Table 6-64.

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DAC Control Register

Figure 6-91 DAC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDACOUT_ENUM_SCALINGDACOUT_SCALING
R-0hW-8hW-8h
15141312111098
DACOUT_SCALINGDACOUT_UNIPOLARDACOUT_VAR_ADDR
W-8hW-0hR/W-0h
76543210
DACOUT_VAR_ADDR
R/W-0h
Table 6-64 DAC Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h Reserved
20-17DACOUT_ENUM_SCALINGW8h Multiplication Factor for DACOUT Algorithm variable extracted from the address contained in DACOUT_VAR_ADDR multiplied with 2DACOUT_ENUM_SCALING. DACOUT_ENUM_SCALING comes into effect only if DACOUT_SCALING is zero
16-13DACOUT_SCALINGW8h Scaling factor for DACOUT Algorithm variable extracted from the address contained in DACOUT_VAR_ADDR scaled with DACOUT_SCALING / 8. Actual voltage depends on DACOUT_UNIPOLAR. If DACOUT_UNIPOLAR = 1b, 0V == 0pu of algorithmVariable * DACOUT_SCALING / 8, 3V == 1pu of algorithmVariable * DACOUT_SCALING / 8 If DACOUT_UNIPOLAR = 0b, 0V == -1pu of algorithmVariable * DACOUT_SCALING / 8, 3V == 1pu of algorithmVariable * DACOUT_SCALING / 8
0h = Treated s Enum with max value being 31
1h = 1 / 8
2h = 2 / 8
3h = 3 / 8
4h = 4 / 8
5h = 5 / 8
6h = 6 / 8
7h = 7 / 8
8h = 8 / 8
9h = 9 / 8
Ah = 10 / 8
Bh = 11 / 8
Ch = 12 / 8
Dh = 13 / 8
Eh = 14 / 8
Fh = 15 / 8
12DACOUT_UNIPOLARW0h Configures output of DACOUT If DACOUT_UNIPOLAR = 1, 0V == 0pu of algorithmVariable * DACOUT_SCALING / 16, 3V == 1pu of algorithmVariable * DACOUT_SCALING / 16 If DACOUT_UNIPOLAR = 0, 0V == -1pu of algorithmVariable * DACOUT_SCALING / 16, 3V == 1pu of algorithmVariable * DACOUT_SCALING / 16
0h = Bipolar (Offset of 1.5 V)
1h = Unipolar (No Offset)
11-0DACOUT_VAR_ADDRR/W0h 12-bit address of variable to be monitored