SLAS697E March   2010  – November 2016 MSP430F2619S-HT


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configurations and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
    3. 3.3 Bare Die Information
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Active-Mode Supply Current Into AVCC Excluding External Current - Electrical Characteristics
    6. 4.6  Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
    7. 4.7  Active-Mode Current vs DCO Frequency
    8. 4.8  Low-Power-Mode Supply Currents Into AVCC Excluding External Current - Electrical Characteristics
    9. 4.9  Typical Characteristics - LPM4 Current
    10. 4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and XT2IN) - Electrical Characteristics
    11. 4.11 Inputs (Ports P1 and P2) - Electrical Characteristics
    12. 4.12 Leakage Current (Ports P1 Through P6) - Electrical Characteristics
    13. 4.13 Standard Inputs - RST/NMI - Electrical Characteristics
    14. 4.14 Outputs (Ports P1 Through P6) - Electrical Characteristics
    15. 4.15 Output Frequency (Ports P1 Through P6) - Electrical Characteristics
    16. 4.16 Typical Characteristics - Outputs
    17. 4.17 POR/Brownout Reset (BOR) - Electrical Characteristics
    18. 4.18 Typical Characteristics - POR/Brownout Reset (BOR)
    19. 4.19 SVS (Supply Voltage Supervisor/Monitor) - Electrical Characteristics
    20. 4.20 Typical Characteristics - SVS
    21. 4.21 Main DCO Characteristics
    22. 4.22 DCO Frequency - Electrical Characteristics
    23. 4.23 Calibrated DCO Frequencies (Tolerance at Calibration) - Electrical Characteristics
    24. 4.24 Calibrated DCO Frequencies (Tolerance Over Temperature) - Electrical Characteristics
    25. 4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage VCC) - Electrical Characteristics
    26. 4.26 Calibrated DCO Frequencies (Overall Tolerance) - Electrical Characteristics
    27. 4.27 Typical Characteristics - Calibrated DCO Frequency
    28. 4.28 Wake-Up From Low-Power Modes (LPM3/4) - Electrical Characteristics
    29. 4.29 Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
    30. 4.30 DCO With External Resistor ROSC - Electrical Characteristics
    31. 4.31 Typical Characteristics - DCO With External Resistor ROSC
    32. 4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes - Electrical Characteristics
    33. 4.33 Internal Very-Low-Power, Low-Frequency Oscillator (VLO) - Electrical Characteristics
    34. 4.34 Crystal Oscillator (LFXT1) High Frequency Modes - Electrical Characteristics
    35. 4.35 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
    36. 4.36 Crystal Oscillator (XT2) - Electrical Characteristics
    37. 4.37 Typical Characteristics - XT2 Oscillator
    38. 4.38 Timer_A - Electrical Characteristics
    39. 4.39 Timer_B - Electrical Characteristics
    40. 4.40 USCI (UART Mode) - Electrical Characteristics
    41. 4.41 USCI (SPI Master Mode) - Electrical Characteristics
    42. 4.42 USCI (SPI Slave Mode) - Electrical Characteristics
    43. 4.43 USCI (I2C Mode) - Electrical Characteristics
    44. 4.44 Comparator_A+ - Electrical Characteristics
    45. 4.45 Typical Characteristics - Comparator A+
    46. 4.46 12-Bit ADC Power-Supply and Input Range Conditions - Electrical Characteristics
    47. 4.47 12-Bit ADC External Reference - Electrical Characteristics
    48. 4.48 12-Bit ADC Built-In Reference - Electrical Characteristics
    49. 4.49 Typical Characteristics - ADC12
    50. 4.50 12-Bit ADC Timing Parameters - Electrical Characteristics
    51. 4.51 12-Bit ADC Linearity Parameters - Electrical Characteristics
    52. 4.52 12-Bit ADC Temperature Sensor and Built-In VMID - Electrical Characteristics
    53. 4.53 12-Bit DAC Supply Specifications - Electrical Characteristics
    54. 4.54 12-Bit DAC Linearity Parameters - Electrical Characteristics
    55. 4.55 Typical Characteristics - 12-Bit DAC Linearity Specifications
    56. 4.56 12-Bit DAC Output Specifications - Electrical Characteristics
    57. 4.57 12-Bit DAC Reference Input Specifications - Electrical Characteristics
    58. 4.58 12-Bit DAC Dynamic Specifications, VREF = VCC, DAC12IR = 1 - Electrical Characteristics
    59. 4.59 Flash Memory - Electrical Characteristics
    60. 4.60 RAM - Electrical Characteristics
    61. 4.61 JTAG and Spy-Bi-Wire Interface - Electrical Characteristics
    62. 4.62 JTAG Fuse - Electrical Characteristics
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Instruction Set
    3. 5.3  Operating Modes
    4. 5.4  Interrupt Vector Addresses
    5. 5.5  Special Function Registers
      1. 5.5.1 Interrupt Enable 1 and 2
      2. 5.5.2 Interrupt Flag Register 1 and 2
    6. 5.6  Memory Organization
    7. 5.7  Bootstrap Loader (BSL)
    8. 5.8  Flash Memory
    9. 5.9  Peripherals
    10. 5.10 DMA Controller
    11. 5.11 Oscillator and System Clock
    12. 5.12 Brownout, Supply Voltage Supervisor (SVS)
    13. 5.13 Digital I/O
    14. 5.14 WDT+ Watchdog Timer
    15. 5.15 Hardware Multiplier
    16. 5.16 USCI
    17. 5.17 Timer_A3
    18. 5.18 Timer_B7
    19. 5.19 Comparator_A+
    20. 5.20 ADC12
    21. 5.21 DAC12
    22. 5.22 Peripheral File Map
  6. 6Applications, Implementation, and Layout
    1. 6.1  P1.0 to P1.7, Input/Output With Schmitt Trigger
    2. 6.2  P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger
    3. 6.3  P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
    4. 6.4  Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
    5. 6.5  Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger
    6. 6.6  Port P5 Pin Schematic: P5.0 to P5.7, Input/Output With Schmitt Trigger
    7. 6.7  Port P6 Pin Schematic: P6.0 to P6.4, Input/Output With Schmitt Trigger
    8. 6.8  Port P6 Pin Schematic: P6.5 and P6.6, Input/Output With Schmitt Trigger
    9. 6.9  Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger
    10. 6.10 Port P7 Pin Schematic: P7.0 to P7.7, Input/Output With Schmitt Trigger
    11. 6.11 Port P8 Pin Schematic: P8.0 to P8.5, Input/Output With Schmitt Trigger
    12. 6.12 Port P8 Pin Schematic: P8.6, Input/Output With Schmitt Trigger
    13. 6.13 Port P8 Pin Schematic: P8.7, Input/Output With Schmitt Trigger
    14. 6.14 JTAG Pins: TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger
    15. 6.15 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Development Tool Support
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 5-1 shows examples of the three types of instruction formats; the address modes are listed in Table 5-2.

MSP430F2619S-HT arch_las530.gif

Table 5-1 Instruction Word Formats

Dual operands, source-destination For example, ADD R4,R5 R4 + R5 → R5
Single operands, destination only For example, CALL R8 PC → (TOS), R8 → PC
Relative jump, un/conditional For example, JNE Jump-on-equal bit = 0

Table 5-2 Address Mode Descriptions

Register MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) MOV EDE,TONI M(EDE) → M(TONI)
Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2 → R10
Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI)
S = source
D = destination

Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

  • Active mode ( AM)
    • All clocks are active.
  • Low-power mode 0 (LPM0)
    • CPU is disabled.
    • ACLK and SMCLK remain active. MCLK is disabled.
  • Low-power mode 1 (LPM1)
    • CPU is disabled.
    • ACLK and SMCLK remain active. MCLK is disabled.
    • DCO’s DC generator is disabled if DCO not used in active mode.
  • Low-power mode 2 (LPM2)
    • CPU is disabled.
    • MCLK and SMCLK are disabled.
    • DCO's dc-generator remains enabled.
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled.
    • MCLK and SMCLK are disabled.
    • DCO's dc-generator is disabled.
    • ACLK remains active.
  • Low-power mode 4 (LPM4)
    • CPU is disabled.
    • ACLK is disabled.
    • MCLK and SMCLK are disabled.
    • DCO's dc-generator is disabled.
    • Crystal oscillator is stopped.

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFF–0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power up.

Power up
External reset
Flash key violation
PC out-of-range(1)
Reset 0x0FFFE 31, highest
Oscillator fault
Flash memory access violation
0x0FFFC 30
Timer_B7 TBCCR0 CCIFG(3) maskable 0x0FFFA 29
Timer_B7 TBCCR1 and TBCCR2
maskable 0x0FFF8 28
Comparator_A+ CAIFG maskable 0x0FFF6 27
Watchdog timer+ WDTIFG maskable 0x0FFF4 26
Timer_A3 TACCR0 CCIFG(3) maskable 0x0FFF2 25
maskable 0x0FFF0 24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG(2)(4) maskable 0x0FFEE 23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG(2)(5) maskable 0x0FFEC 22
ADC12 ADC12IFG(3) maskable 0x0FFEA 21
0x0FFE8 20
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7(2)(3) maskable 0x0FFE6 19
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7(2)(3) maskable 0x0FFE4 18
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
UCA1RXIFG, UCB1RXIFG(2)(4) maskable 0x0FFE2 17
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG(2)(5) maskable 0x0FFE0 16
DMA DMA0IFG, DMA1IFG, DMA2IFG(2)(3) maskable 0x0FFDE 15
DAC12 DAC12_0IFG, DAC12_1IFG(2)(3) maskable 0x0FFDC 14
Reserved(7)(8) Reserved 0x0FFDA to 0x0FFC0 13 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x00000 – 0x001FF) or from within unused address range.
Multiple source flags
Interrupt flags are located in the module.
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY). A 0x0AA55 at this location disables the BSL completely. A zero disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0x0FFDC to 0x0FFC0 are not used in this device and can be used for regular program code if necessary.

Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Interrupt Enable 1 and 2

Address 7 6 5 4 3 2 1 0
rw-0 rw-0 rw-0 rw-0
WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode.
OFIE: Oscillator fault enable
NMIIE: (Non)maskable interrupt enable
ACCVIE: Flash access violation interrupt enable
Address 7 6 5 4 3 2 1 0
rw-0 rw-0 rw-0 rw-0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable

Interrupt Flag Register 1 and 2

Address 7 6 5 4 3 2 1 0
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault7
RSTIFG: External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
PORIFG: Power-On Reset interrupt flag. Set on VCC power up.
NMIIFG: Set via RST/NMI-pin
Address 7 6 5 4 3 2 1 0
03h UCB0
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag


rw: Bit can be read and written.
rw-0, 1: Bit can be read and written. It is Reset or Set by PUC.
rw-(0), (1): Bit can be read and written. It is Reset or Set by POR.
MSP430F2619S-HT shd-cell_slas530.gif SFR bit is not present in device.

Memory Organization

Main: interrupt vector
Main: code memory
120 kB Flash
0x0FFFF – 0x0FFC0
0x0FFFF – 0x02100
RAM (total) Size 4 kB
0x020FF -- 0x01100
Extended Size 2 kB
0x020FF -- 0x01900
Mirrored Size 2 kB
0x018FF -- 0x01100
Information memory Size
256 Byte
0x010FF – 0x01000
Boot memory Size
1 kB
0x0FFF – 0x0C00
RAM (mirrored at 18FFh to 01100h) Size 2 kB
0x009FF – 0x0200
Peripherals 16-bit
8-bit SFR
0x001FF – 0x00100
0x000FF – 0x00010
0x0000F – 0x00000

Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see Features of the MSP430 Bootstrap Loader (SLAA089).

BSL Function PM Package Pins
Data Transmit 13 - P1.1
Data Receive 22 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A to D can be erased individually, or as a group with segments 0–n.
    Segments A to D are also called information memory.
  • Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.
  • Flash content integrity check with marginal read modes.


Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to MSP430x2xx Family User's Guide (SLAU144).

DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversionmemory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator for –55°C to 105°C operation. For > 105°C, use external clock source.
  • Main clock (MCLK), the system clock used by the CPU
  • Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

Table 5-3 Tags Used by the TLV Structure

TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration
TAG_ADC12_1 0x10DA 0x08 ADC12_1 calibration tag
TAG_EMPTY -- 0xFE Identifier for empty areas

Table 5-4 Labels Used by the ADC Calibration Structure

CAL_ADC_25T85 INCHx = 0x1010; REF2_5 = 1, TA = 125°C word 0x000E
CAL_ADC_25T30 INCHx = 0x1010; REF2_5 = 1, TA = 30°C word 0x000C
CAL_ADC_25VREF_FACTOR REF2_5 = 1,TA = 30°C word 0x000A
CAL_ADC_15T85 INCHx = 0x1010; REF2_5 = 0, TA = 125°C word 0x0008
CAL_ADC_15T30 INCHx = 0x1010; REF2_5 = 0, TA = 30°C word 0x0006
CAL_ADC_15VREF_FACTOR REF2_5 = 0,TA = 30°C word 0x0004
CAL_ADC_OFFSET External VREF = 1.5 V, ƒADC12CLK = 5 MHz word 0x0002
CAL_ADC_GAIN_FACTOR External VREF = 1.5 , ƒADC12CLK = 5 MHz word 0x0000
CAL_BC1_1MHZ -- byte 0x0007
CAL_DCO_1MHZ -- byte 0x0006
CAL_BC1_8MHZ -- byte 0x0005
CAL_DCO_8MHZ -- byte 0x0004
CAL_BC1_12MHZ -- byte 0x0003
CAL_DCO_12MHZ -- byte 0x0002
CAL_BC1_16MHZ -- byte 0x0001
CAL_DCO_16MHZ -- byte 0x0000

Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

Digital I/O

There are six 8-bit I/O ports implemented – ports P1 through P6:

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt condition is possible.
  • Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
  • Read/write access to port-control registers is supported by all instructions.
  • Each I/O has an individually programmable pullup/pulldown resistor.

WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16 × 16,
16 × 8, 8 × 16, and 8 × 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.


The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baud-rate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.


Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 5-5 TIMER_A3 Signal Connections

12 - P1.0 TACLK TACLK Timer NA
13 - P1.1 TA0 CCI0A CCR0 TA0 13 - P1.1
22 - P2.2 TA0 CCI0B 17 - P1.5
DVSS GND 27 - P2.7
14 - P1.2 TA1 CCI1A CCR1 TA1 14 - P1.2
CCI1B 18 - P1.6
DVSS GND 23 - P2.3
15 - P1.3 TA2 CCI2A CCR2 TA2 15 - P1.3
CCI2B 19 - P1.7
DVSS GND 24 - P2.4


Timer_B7 is a 16-bit timer/counter with three capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer_B7 Signal Connections
43 - P4.7 TBCLK TBCLK Timer NA
36 - P4.0 TB0 CCI0A CCR0 TB0 36 - P4.0
36 - P4.0 TB0 CCI0B ADC12 (internal)
37 - P4.1 TB1 CCI1A CCR1 TB1 37 - P4.1
37 - P4.1 TB1 CCI1B ADC12 (internal)
38 - P4.2 TB2 CCI2A CCR2 TB2 38 - P4.2
38 - P4.2 TB2 CCI2B DAC_0
39 - P4.3 TB3 CCI3A CCR3 TB3 39 - P4.3
39 - P4.3 TB3 CCI3B
40 - P4.4 TB4 CCI4A CCR4 TB4 40 - P4.4
40 - P4.4 TB4 CCI4B
41 - P4.5 TB5 CCI5A CCR5 TB5 41 - P4.5
41 - P4.5 TB5 CCI5B
42 - P4.6 TB6 CCI6A CCR6 TB6 42 - P4.6
ACLK (internal) CCI6B


The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.


The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.


The DAC12 module is a 12-bit, R-ladder, voltage-output digital-to-analog converter (DAC). The DAC12 may be used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

Peripheral File Map

DMA DMA channel 2 transfer size DMA2SZ 0x01F2
DMA channel 2 destination address DMA2DA 0x01EE
DMA channel 2 source address DMA2SA 0x01EA
DMA channel 2 control DMA2CTL 0x01E8
DMA channel 1 transfer size DMA1SZ 0x01E6
DMA channel 1 destination address DMA1DA 0x01E2
DMA channel 1 source address DMA1SA 0x01DE
DMA channel 1 control DMA1CTL 0x01DC
DMA channel 0 transfer size DMA0SZ 0x01DA
DMA channel 0 destination address DMA0DA 0x01D6
DMA channel 0 source address DMA0SA 0x01D2
DMA channel 0 control DMA0CTL 0x01D0
DMA module interrupt vector word DMAIV 0x0126
DMA module control 1 DMACTL1 0x0124
DMA module control 0 DMACTL0 0x0122
DAC12 DAC12_1 data DAC12_1DAT 0x01CA
DAC12_1 control DAC12_1CTL 0x01C2
DAC12_0 data DAC12_0DAT 0x01C8
DAC12_0 control DAC12_0CTL 0x01C0
ADC12 Interrupt-vector-word register ADC12IV 0x01A8
Interrupt-enable register ADC12IE 0x01A6
Interrupt-flag register ADC12IFG 0x01A4
Control register 1 ADC12CTL1 0x01A2
Control register 0 ADC12CTL0 0x01A0
Conversion memory 15 ADC12MEM15 0x015E
Conversion memory 14 ADC12MEM14 0x015C
Conversion memory 13 ADC12MEM13 0x015A
Conversion memory 12 ADC12MEM12 0x0158
Conversion memory 11 ADC12MEM11 0x0156
Conversion memory 10 ADC12MEM10 0x0154
Conversion memory 9 ADC12MEM9 0x0152
Conversion memory 8 ADC12MEM8 0x0150
Conversion memory 7 ADC12MEM7 0x014E
Conversion memory 6 ADC12MEM6 0x014C
ADC12 Conversion memory 5 ADC12MEM5 0x014A
Conversion memory 4 ADC12MEM4 0x0148
Conversion memory 3 ADC12MEM3 0x0146
Conversion memory 2 ADC12MEM2 0x0144
Conversion memory 1 ADC12MEM1 0x0142
Conversion 0 ADC12MEM0 0x0140
ADC memory-control register15 ADC12MCTL15 0x008F
ADC memory-control register14 ADC12MCTL14 0x008E
ADC memory-control register13 ADC12MCTL13 0x008D
ADC memory-control register12 ADC12MCTL12 0x008C
ADC memory-control register11 ADC12MCTL11 0x008B
ADC memory-control register10 ADC12MCTL10 0x008A
ADC memory-control register9 ADC12MCTL9 0x0089
ADC memory-control register8 ADC12MCTL8 0x0088
ADC memory-control register7 ADC12MCTL7 0x0087
ADC memory-control register6 ADC12MCTL6 0x0086
ADC memory-control register5 ADC12MCTL5 0x0085
ADC memory-control register4 ADC12MCTL4 0x0084
ADC memory-control register3 ADC12MCTL3 0x0083
ADC memory-control register2 ADC12MCTL2 0x0082
ADC memory-control register1 ADC12MCTL1 0x0081
ADC memory-control register0 ADC12MCTL0 0x0080
Timer_B7 Capture/compare register _ 6 TBCCR6 0x019E
Capture/compare register 5 TBCCR5 0x019C
Capture/compare register 4 TBCCR4 0x019A
Capture/compare register 3 TBCCR3 0x0198
Capture/compare register 2 TBCCR2 0x0196
Capture/compare register 1 TBCCR1 0x0194
Capture/compare register 0 TBCCR0 0x0192
Timer_B register TBR 0x0190
Capture/compare control 6 TBCCTL6 0x018E
Capture/compare control 5 TBCCTL5 0x018C
Capture/compare control 4 TBCCTL4 0x018A
Capture/compare control 3 TBCCTL3 0x0188
Capture/compare control 2 TBCCTL2 0x0186
Capture/compare control 1 TBCCTL1 0x0184
Capture/compare control 0 TBCCTL0 0x0182
Timer_B control TBCTL 0x0180
Timer_B interrupt vector TBIV 0x011E
Timer_A3 Capture/compare register 2 TACCR2 0x0176
Capture/compare register 1 TACCR1 0x0174
Capture/compare register 0 TACCR0 0x0172
Timer_A register TAR 0x0170
Reserved 0x016E
Reserved 0x016C
Reserved 0x016A
Reserved 0x0168
Capture/compare control 2 TACCTL2 0x0166
Capture/compare control 1 TACCTL1 0x0164
Capture/compare control 0 TACCTL0 0x0162
Timer_A control TACTL 0x0160
Timer_A interrupt vector TAIV 0x012E
Hardware Multiplier Sum extend SUMEXT 0x013E
Result high word RESHI 0x013C
Result low word RESLO 0x013A
Second operand OP2 0x0138
Multiply signed +accumulate/operand1 MACS 0x0136
Multiply+accumulate/operand1 MAC 0x0134
Multiply signed/operand1 MPYS 0x0132
Multiply unsigned/operand1 MPY 0x0130
Flash Flash control 4 FCTL4 0x01BE
Flash control 3 FCTL3 0x012C
Flash control 2 FCTL2 0x012A
Flash control 1 FCTL1 0x0128
Watchdog Watchdog/timer control WDTCTL 0x0120
USCI A0/B0 USCI A0 auto baud rate control UCA0ABCTL 0x005D
USCI A0 transmit buffer UCA0TXBUF 0x0067
USCI A0 receive buffer UCA0RXBUF 0x0066
USCI A0 status UCA0STAT 0x0065
USCI A0 modulation control UCA0MCTL 0x0064
USCI A0 baud rate control 1 UCA0BR1 0x0063
USCI A0 baud rate control 0 UCA0BR0 0x0062
USCI A0 control 1 UCA0CTL1 0x0061
USCI A0 control 0 UCA0CTL0 0x0060
USCI A0 IrDA receive control UCA0IRRCTL 0x005F
USCI A0 IrDA transmit control UCA0IRTCLT 0x005E
USCI B0 transmit buffer UCB0TXBUF 0x006F
USCI B0 receive buffer UCB0RXBUF 0x006E
USCI B0 status UCB0STAT 0x006D
USCI B0 I2C interrupt enable UCB0CIE 0x006C
USCI B0 baud rate control 1 UCB0BR1 0x006B
USCI B0 baud rate control 0 UCB0BR0 0x006A
USCI B0 control 1 UCB0CTL1 0x0069
USCI B0 control 0 UCB0CTL0 0x0068
USCI B0 I2C slave address UCB0SA 0x011A
USCI B0 I2C own address UCB0OA 0x0118
USCI A1/B1 USCI A1 auto baud rate control UCA1ABCTL 0x00CD
USCI A1 transmit buffer UCA1TXBUF 0x00D7
USCI A1 receive buffer UCA1RXBUF 0x00D6
USCI A1 status UCA1STAT 0x00D5
USCI A1 modulation control UCA1MCTL 0x00D4
USCI A1 baud rate control 1 UCA1BR1 0x00D3
USCI A1 baud rate control 0 UCA1BR0 0x00D2
USCI A1 control 1 UCA1CTL1 0x00D1
USCI A1 control 0 UCA1CTL0 0x00D0
USCI A1 IrDA receive control UCA1IRRCTL 0x00CF
USCI A1 IrDA transmit control UCA1IRTCLT 0x00CE
USCI B1 transmit buffer UCB1TXBUF 0x00DF
USCI B1 receive buffer UCB1RXBUF 0x00DE
USCI B1 status UCB1STAT 0x00DD
USCI B1 I2C Interrupt enable UCB1CIE 0x00DC
USCI B1 baud rate control 1 UCB1BR1 0x00DB
USCI B1 baud rate control 0 UCB1BR0 0x00DA
USCI B1 control 1 UCB1CTL1 0x00D9
USCI B1 control 0 UCB1CTL0 0x00D8
USCI B1 I2C slave address UCB1SA 0x017E
USCI B1 I2C own address UCB1OA 0x017C
USCI A1/B1 interrupt enable UC1IE 0x0006
USCI A1/B1 interrupt flag UC1IFG 0x0007
Comparator_A+ Comparator_A port disable CAPD 0x005B
Comparator_A control2 CACTL2 0x005A
Comparator_A control1 CACTL1 0x0059
Basic Clock Basic clock system control3 BCSCTL3 0x0053
Basic clock system control2 BCSCTL2 0x0058
Basic clock system control1 BCSCTL1 0x0057
DCO clock frequency control DCOCTL 0x0056
Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0x0055
Port P6 Port P6 resistor enable P6REN 0x0013
Port P6 selection P6SEL 0x0037
Port P6 direction P6DIR 0x0036
Port P6 output P6OUT 0x0035
Port P6 input P6IN 0x0034
Port P5 Port P5 resistor enable P5REN 0x0012
Port P5 selection P5SEL 0x0033
Port P5 direction P5DIR 0x0032
Port P5 output P5OUT 0x0031
Port P5 input P5IN 0x0030
Port P4 Port P4 selection P4SEL 0x001F
Port P4 resistor enable P4REN 0x0011
Port P4 direction P4DIR 0x001E
Port P4 output P4OUT 0x001D
Port P4 input P4IN 0x001C
Port P3 Port P3 resistor enable P3REN 0x0010
Port P3 selection P3SEL 0x001B
Port P3 direction P3DIR 0x001A
Port P3 output P3OUT 0x0019
Port P3 input P3IN 0x0018
Port P2 Port P2 resistor enable P2REN 0x002F
Port P2 selection P2SEL 0x002E
Port P2 interrupt enable P2IE 0x002D
Port P2 interrupt-edge select P2IES 0x002C
Port P2 interrupt flag P2IFG 0x002B
Port P2 direction P2DIR 0x002A
Port P2 output P2OUT 0x0029
Port P2 input P2IN 0x0028
Port P1 Port P1 resistor enable P1REN 0x0027
Port P1 selection P1SEL 0x0026
Port P1 interrupt enable P1IE 0x0025
Port P1 interrupt-edge select P1IES 0x0024
Port P1 interrupt flag P1IFG 0x0023
Port P1 direction P1DIR 0x0022
Port P1 output P1OUT 0x0021
Port P1 input P1IN 0x0020
Special Functions SFR interrupt flag2 IFG2 0x0003
SFR interrupt flag1 IFG1 0x0002
SFR interrupt enable2 IE2 0x0001
SFR interrupt enable1 IE1 0x0000