SLAS697E March   2010  – November 2016 MSP430F2619S-HT

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configurations and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
    3. 3.3 Bare Die Information
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Active-Mode Supply Current Into AVCC Excluding External Current - Electrical Characteristics
    6. 4.6  Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
    7. 4.7  Active-Mode Current vs DCO Frequency
    8. 4.8  Low-Power-Mode Supply Currents Into AVCC Excluding External Current - Electrical Characteristics
    9. 4.9  Typical Characteristics - LPM4 Current
    10. 4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and XT2IN) - Electrical Characteristics
    11. 4.11 Inputs (Ports P1 and P2) - Electrical Characteristics
    12. 4.12 Leakage Current (Ports P1 Through P6) - Electrical Characteristics
    13. 4.13 Standard Inputs - RST/NMI - Electrical Characteristics
    14. 4.14 Outputs (Ports P1 Through P6) - Electrical Characteristics
    15. 4.15 Output Frequency (Ports P1 Through P6) - Electrical Characteristics
    16. 4.16 Typical Characteristics - Outputs
    17. 4.17 POR/Brownout Reset (BOR) - Electrical Characteristics
    18. 4.18 Typical Characteristics - POR/Brownout Reset (BOR)
    19. 4.19 SVS (Supply Voltage Supervisor/Monitor) - Electrical Characteristics
    20. 4.20 Typical Characteristics - SVS
    21. 4.21 Main DCO Characteristics
    22. 4.22 DCO Frequency - Electrical Characteristics
    23. 4.23 Calibrated DCO Frequencies (Tolerance at Calibration) - Electrical Characteristics
    24. 4.24 Calibrated DCO Frequencies (Tolerance Over Temperature) - Electrical Characteristics
    25. 4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage VCC) - Electrical Characteristics
    26. 4.26 Calibrated DCO Frequencies (Overall Tolerance) - Electrical Characteristics
    27. 4.27 Typical Characteristics - Calibrated DCO Frequency
    28. 4.28 Wake-Up From Low-Power Modes (LPM3/4) - Electrical Characteristics
    29. 4.29 Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
    30. 4.30 DCO With External Resistor ROSC - Electrical Characteristics
    31. 4.31 Typical Characteristics - DCO With External Resistor ROSC
    32. 4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes - Electrical Characteristics
    33. 4.33 Internal Very-Low-Power, Low-Frequency Oscillator (VLO) - Electrical Characteristics
    34. 4.34 Crystal Oscillator (LFXT1) High Frequency Modes - Electrical Characteristics
    35. 4.35 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
    36. 4.36 Crystal Oscillator (XT2) - Electrical Characteristics
    37. 4.37 Typical Characteristics - XT2 Oscillator
    38. 4.38 Timer_A - Electrical Characteristics
    39. 4.39 Timer_B - Electrical Characteristics
    40. 4.40 USCI (UART Mode) - Electrical Characteristics
    41. 4.41 USCI (SPI Master Mode) - Electrical Characteristics
    42. 4.42 USCI (SPI Slave Mode) - Electrical Characteristics
    43. 4.43 USCI (I2C Mode) - Electrical Characteristics
    44. 4.44 Comparator_A+ - Electrical Characteristics
    45. 4.45 Typical Characteristics - Comparator A+
    46. 4.46 12-Bit ADC Power-Supply and Input Range Conditions - Electrical Characteristics
    47. 4.47 12-Bit ADC External Reference - Electrical Characteristics
    48. 4.48 12-Bit ADC Built-In Reference - Electrical Characteristics
    49. 4.49 Typical Characteristics - ADC12
    50. 4.50 12-Bit ADC Timing Parameters - Electrical Characteristics
    51. 4.51 12-Bit ADC Linearity Parameters - Electrical Characteristics
    52. 4.52 12-Bit ADC Temperature Sensor and Built-In VMID - Electrical Characteristics
    53. 4.53 12-Bit DAC Supply Specifications - Electrical Characteristics
    54. 4.54 12-Bit DAC Linearity Parameters - Electrical Characteristics
    55. 4.55 Typical Characteristics - 12-Bit DAC Linearity Specifications
    56. 4.56 12-Bit DAC Output Specifications - Electrical Characteristics
    57. 4.57 12-Bit DAC Reference Input Specifications - Electrical Characteristics
    58. 4.58 12-Bit DAC Dynamic Specifications, VREF = VCC, DAC12IR = 1 - Electrical Characteristics
    59. 4.59 Flash Memory - Electrical Characteristics
    60. 4.60 RAM - Electrical Characteristics
    61. 4.61 JTAG and Spy-Bi-Wire Interface - Electrical Characteristics
    62. 4.62 JTAG Fuse - Electrical Characteristics
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Instruction Set
    3. 5.3  Operating Modes
    4. 5.4  Interrupt Vector Addresses
    5. 5.5  Special Function Registers
      1. 5.5.1 Interrupt Enable 1 and 2
      2. 5.5.2 Interrupt Flag Register 1 and 2
    6. 5.6  Memory Organization
    7. 5.7  Bootstrap Loader (BSL)
    8. 5.8  Flash Memory
    9. 5.9  Peripherals
    10. 5.10 DMA Controller
    11. 5.11 Oscillator and System Clock
    12. 5.12 Brownout, Supply Voltage Supervisor (SVS)
    13. 5.13 Digital I/O
    14. 5.14 WDT+ Watchdog Timer
    15. 5.15 Hardware Multiplier
    16. 5.16 USCI
    17. 5.17 Timer_A3
    18. 5.18 Timer_B7
    19. 5.19 Comparator_A+
    20. 5.20 ADC12
    21. 5.21 DAC12
    22. 5.22 Peripheral File Map
  6. 6Applications, Implementation, and Layout
    1. 6.1  P1.0 to P1.7, Input/Output With Schmitt Trigger
    2. 6.2  P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger
    3. 6.3  P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
    4. 6.4  Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
    5. 6.5  Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger
    6. 6.6  Port P5 Pin Schematic: P5.0 to P5.7, Input/Output With Schmitt Trigger
    7. 6.7  Port P6 Pin Schematic: P6.0 to P6.4, Input/Output With Schmitt Trigger
    8. 6.8  Port P6 Pin Schematic: P6.5 and P6.6, Input/Output With Schmitt Trigger
    9. 6.9  Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger
    10. 6.10 Port P7 Pin Schematic: P7.0 to P7.7, Input/Output With Schmitt Trigger
    11. 6.11 Port P8 Pin Schematic: P8.0 to P8.5, Input/Output With Schmitt Trigger
    12. 6.12 Port P8 Pin Schematic: P8.6, Input/Output With Schmitt Trigger
    13. 6.13 Port P8 Pin Schematic: P8.7, Input/Output With Schmitt Trigger
    14. 6.14 JTAG Pins: TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger
    15. 6.15 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Development Tool Support
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configurations and Functions

3.1 Pin Diagram

Figure 3-1 64-Pin PM Package (Top View)

3.2 Pin Attributes

Table 3-1 Pin Attributes (64-PM Package)

PIN I/O DESCRIPTION
NAME PM
AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DVCC1 1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1 63 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/CAOUT 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input/Comparator_A output
P1.1/TA0 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 I/O General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2 20 I/O General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/CA3 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0/CA4 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive/Comparator_A input
P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc/CA5 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency/Comparator_A input
P2.6/ADC12CLK/DMAE0/CA6 26 I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger/Comparator_A input
P2.7/TA0/CA7 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A input
P3.0/UCB0STE/UCA0CLK 28 I/O General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0 clock input/output
P3.1/UCB0SIMO/UCB0SDA 29 I/O General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
P3.2/UCB0SOMI/UCB0SCL 30 I/O General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.3/UCB0CLK/UCA0STE 31 I/O General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/UCA0TXD/UCA0SIMO 32 I/O General-purpose digital I/O pin/USCIA transmit data output in UART mode, slave data in/master out in SPI mode
P3.5/UCA0RXD/UCA0SOMI 33 I/O General-purpose digital I/O pin/USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
P3.6/UCA1TXD/UCA1SIMO 34 I/O General-purpose digital I/O pin/USCI A1 transmit data output in UART mode, slave data in/master out in SPI mode
P3.7/UCA1RXD/UCA1SOMI 35 I/O General-purpose digital I/O pin/USCIA1 receive data input in UART mode, slave data out/master in in SPI mode
P4.0/TB0 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/UCB1STE/UCA1CLK 44 I/O General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1 clock input/output
P5.1/UCB1SIMO/UCB1SDA 45 I/O General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode, SDA I2C data in I2C mode
P5.2/UCB1SOMI/UCB1SCL 46 I/O General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode, SCL I2C clock in I2C mode
P5.3/UCB1CLK/UCA1STE 47 I/O General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave transmit enable
P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/SVSOUT 51 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB6/SVS comparator output
P6.0/A0 59 I/O General-purpose digital I/O pin/analog input A0 – 12-bit ADC
P6.1/A1 60 I/O General-purpose digital I/O pin/analog input A1 – 12-bit ADC
P6.2/A2 61 I/O General-purpose digital I/O pin/analog input A2 – 12-bit ADC
P6.3/A3 2 I/O General-purpose digital I/O pin/analog input A3 – 12-bit ADC
P6.4/A4 3 I/O General-purpose digital I/O pin/analog input A4 – 12-bit ADC
P6.5/A5/DAC1 4 I/O General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1 output
P6.6/A6/DAC0 5 I/O General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0 output
P6.7/A7/DAC1/SVSIN 6 I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
P7.0 NC I/O General-purpose digital I/O pin
P7.1 NC I/O General-purpose digital I/O pin
P7.2 NC I/O General-purpose digital I/O pin
P7.3 NC I/O General-purpose digital I/O pin
P7.4 NC I/O General-purpose digital I/O pin
P7.5 NC I/O General-purpose digital I/O pin
P7.6 NC I/O General-purpose digital I/O pin
P7.7 NC I/O General-purpose digital I/O pin
P8.0 NC I/O General-purpose digital I/O pin
P8.1 NC I/O General-purpose digital I/O pin
P8.2 NC I/O General-purpose digital I/O pin
P8.3 NC I/O General-purpose digital I/O pin
P8.4 NC I/O General-purpose digital I/O pin
P8.5 NC I/O General-purpose digital I/O pin
P8.6/XT2OUT NC O General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
P8.7/XT2IN NC I General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT 52 O Output terminal of crystal oscillator XT2
XT2IN 53 I Input port for crystal oscillator XT2
RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices)
TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
VeREF+/DAC0 10 I Input for an external reference voltage/DAC12.0 output
VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12
VREF–/VeREF– 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

3.3 Bare Die Information

DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS
10.5 mils Silicon with backgrind Floating TiN/AlCu.5% 800 nm
MSP430F2619S-HT die_slas697.gif

Table 3-2 Bond Pad Coordinates in Microns (64-Pin MSP430F2619S64KGD1)

DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX
AVCC 1 90.65 4729.1 165.65 4804.1
DVCC1 2 90.65 4586.85 165.65 4661.85
P6.3/A3 3 87.4 4440.3 162.4 4515.3
P6.4/A4 4 87.4 4282.65 162.4 4357.65
P6.5/A5/DAC1 5 87.4 4125.05 162.4 4200.05
P6.6/A6/DAC0 6 87.4 3943.9 162.4 4018.9
P6.7/A7/DAC1/SVSIN 7 87.4 3762.75 162.4 3837.75
VREF+ 8 92.95 3524.75 167.95 3599.75
XIN 9 87.4 3346.6 162.4 3421.6
XOUT 10 87.4 2472.4 162.4 2547.4
VeREF+/DAC0 11 92.95 2251 167.95 2326
VREF-/VeREF- 12 92.95 2082.5 167.95 2157.5
P1.0/TACLK/CAOUT 13 87.4 1866.2 162.4 1941.2
N/C 14 87.4 1730.6 162.4 1805.6
N/C 15 87.4 1595 162.4 1670
N/C 16 87.4 1459.4 162.4 1534.4
N/C 17 87.4 1323.8 162.4 1398.8
P1.1/TA0 18 87.4 1188.2 162.4 1263.2
P1.2/TA1 19 87.4 1052.6 162.4 1127.6
P1.3/TA2 20 87.4 807.7 162.4 882.7
P1.4/SMCLK 21 87.4 672.1 162.4 747.1
P1.5/TA0 22 559.1 87.4 634.1 162.4
P1.6/TA1 23 694.7 87.4 769.7 162.4
P1.7/TA2 24 830.3 87.4 905.3 162.4
P2.0/ACLK/CA2 25 1234.9 87.4 1309.9 162.4
P2.1/TAINCLK/CA3 26 1370.5 87.4 1445.5 162.4
P2.2/CAOUT/TA0/CA4 27 1506.1 87.4 1581.1 162.4
N/C 28 1641.7 87.4 1716.7 162.4
N/C 29 1777.3 87.4 1852.3 162.4
N/C 30 1912.9 87.4 1987.9 162.4
N/C 31 2053 87.4 2128 162.4
P2.3/CA0/TA1 32 2193.1 87.4 2268.1 162.4
P2.4/CA1/TA2 33 2328.7 87.4 2403.7 162.4
P2.5/ROSC/CA5 34 2464.3 87.4 2539.3 162.4
P2.6/ADC12CLK/DMAE0/CA6 35 2671.1 87.4 2746.1 162.4
P2.7/TA0/CA7 36 2807.15 87.4 2882.15 162.4
P3.0/UCB0STE/UCA0CLK 37 3585.9 87.4 3660.9 162.4
P3.1/UCB0SIMO/UCB0SDA 38 3721.5 87.4 3796.5 162.4
P3.2/UCB0SOMI/UCB0SCL 39 3861.6 87.4 3936.6 162.4
P3.3/UCB0CLK/UCA0STE 40 4001.7 87.4 4076.7 162.4
P3.4/UCA0TXD/UCA0SIMO 41 4137.3 87.4 4212.3 162.4
P3.5/UCA0RXD/UCA0SOMI 42 4887.6 669.65 4962.6 744.65
P3.6/UCA1TXD/UCA1SIMO 43 4887.6 805.25 4962.6 880.25
P3.7/UCA1RXD/UCA1SOMI 44 4887.6 940.85 4962.6 1015.85
N/C 45 4887.6 1076.45 4962.6 1151.45
N/C 46 4887.6 1212.05 4962.6 1287.05
P4.0/TB0 47 4887.6 1352.15 4962.6 1427.15
P4.1/TB1 48 4887.6 1492.25 4962.6 1567.25
P4.2/TB2 49 4887.6 1627.85 4962.6 1702.85
P4.3/TB3 50 4887.6 2533.55 4962.6 2608.55
P4.4/TB4 51 4887.6 2669.15 4962.6 2744.15
P4.5/TB5 52 4887.6 2804.75 4962.6 2879.75
N/C 53 4884.35 2953.25 4959.35 3028.25
N/C 54 4887.6 3060.45 4962.6 3135.45
P4.6/TB6 55 4887.6 3153.45 4962.6 3228.45
P4.7/TBCLK 56 4887.6 3289.05 4962.6 3364.05
P5.0/UCB1STE/UCA1CLK 57 4887.6 3424.65 4962.6 3499.65
P5.1/UCB1SIMO/UCB1SDA 58 4887.6 3560.25 4962.6 3635.25
P5.2/UCB1SOMI/UCB1SCL 59 4887.6 3700.35 4962.6 3775.35
P5.3/UCB1CLK/UCA1STE 60 4887.6 3840.45 4962.6 3915.45
P5.4/MCLK 61 4887.6 3997.05 4962.6 4072.05
P5.5/SMCLK 62 4237.65 4887.6 4312.65 4962.6
P5.6/ACLK 63 4102.05 4887.6 4177.05 4962.6
P5.7/TBOUTH/SVSOUT 64 3966.45 4887.6 4041.45 4962.6
N/C 65 3830.85 4887.6 3905.85 4962.6
N/C 66 3547.7 4887.6 3622.7 4962.6
N/C 67 3412.1 4887.6 3487.1 4962.6
N/C 68 3276.5 4887.6 3351.5 4962.6
XT2OUT 69 3140.9 4887.6 3215.9 4962.6
XT2IN 70 2992.85 4887.6 3067.85 4962.6
TDO/TDI 71 2844.6 4887.6 2919.6 4962.6
TDI/TCLK 72 2448 4887.6 2523 4962.6
TMS 73 2152.25 4887.6 2227.25 4962.6
TCK 74 1568.55 4887.6 1643.55 4962.6
RST/NMI 75 1431.85 4887.6 1506.85 4962.6
P6.0/A0 76 1230.75 4887.6 1305.75 4962.6
P6.1/A1 77 1077.9 4887.6 1152.9 4962.6
P6.2/A2 78 923.95 4887.6 998.95 4962.6
AVSS 79 821.05 4887.95 896.05 4962.95
AVSS 80 674.95 4887.6 749.95 4962.6
DVSS1 81 499.2 4887.6 574.2 4962.6
AVCC 82 337.85 4884.35 412.85 4959.35

Table 3-3 Bond Pad Coordinates in Microns (80-Pin MSP430F2619SKGD1)

DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX
AVCC 1 90.65 4729.1 165.65 4804.1
DVCC1 2 90.65 4586.85 165.65 4661.85
P6.3/A3 3 87.4 4440.3 162.4 4515.3
P6.4/A4 4 87.4 4282.65 162.4 4357.65
P6.5/A5/DAC1 5 87.4 4125.05 162.4 4200.05
P6.6/A6/DAC0 6 87.4 3943.9 162.4 4018.9
P6.7/A7/DAC1/SVSIN 7 87.4 3762.75 162.4 3837.75
VREF+ 8 92.95 3524.75 167.95 3599.75
XIN 9 87.4 3346.6 162.4 3421.6
XOUT 10 87.4 2472.4 162.4 2547.4
VeREF+/DAC0 11 92.95 2251 167.95 2326
VREF-/VeREF- 12 92.95 2082.5 167.95 2157.5
P1.0/TACLK/CAOUT 13 87.4 1866.2 162.4 1941.2
P1.1/TA0 14 87.4 1730.6 162.4 1805.6
P1.2/TA1 15 87.4 1595 162.4 1670
P1.3/TA2 16 87.4 1459.4 162.4 1534.4
P1.4/SMCLK 17 87.4 1323.8 162.4 1398.8
P1.5/TA0 18 87.4 1188.2 162.4 1263.2
P1.6/TA1 19 87.4 1052.6 162.4 1127.6
P1.7/TA2 20 87.4 807.7 162.4 882.7
P2.0/ACLK/CA2 21 87.4 672.1 162.4 747.1
P2.1/TAINCLK/CA3 22 559.1 87.4 634.1 162.4
P2.2/CAOUT/TA0/CA4 23 694.7 87.4 769.7 162.4
P2.3/CA0/TA1 24 830.3 87.4 905.3 162.4
P2.4/CA1/TA2 25 1234.9 87.4 1309.9 162.4
P2.5/Rosc/CA5 26 1370.5 87.4 1445.5 162.4
P2.6/ADC12CLK/DMAE0/CA6 27 1506.1 87.4 1581.1 162.4
P2.7/TA0/CA7 28 1641.7 87.4 1716.7 162.4
P3.0/UCB0STE/UCA0CLK 29 1777.3 87.4 1852.3 162.4
P3.1/UCB0SIMO/UCB0SDA 30 1912.9 87.4 1987.9 162.4
P3.2/UCBOSOMI/UCB0SCL 31 2053 87.4 2128 162.4
P3.3/UCB0CLK/UCA0STE 32 2193.1 87.4 2268.1 162.4
P3.4/UCA0TXD/UCA0SIMO 33 2328.7 87.4 2403.7 162.4
P3.5/UCA0RXD/UCA0SOMI 34 2464.3 87.4 2539.3 162.4
P3.6/UCA1TXD/UCA1SIMO 35 2671.1 87.4 2746.1 162.4
P3.7/UCA1RXD/UCA1SOMI 36 2807.15 87.4 2882.15 162.4
P4.0/TB0 37 3585.9 87.4 3660.9 162.4
P4.1/TB1 38 3721.5 87.4 3796.5 162.4
P4.2/TB2 39 3861.6 87.4 3936.6 162.4
P4.3/TB3 40 4001.7 87.4 4076.7 162.4
P4.4/TB4 41 4137.3 87.4 4212.3 162.4
P4.5/TB5 42 4887.6 669.65 4962.6 744.65
P4.6/TB6 43 4887.6 805.25 4962.6 880.25
P4.7/TBCLK 44 4887.6 940.85 4962.6 1015.85
P5.0/UCB1STE/UCA1CLK 45 4887.6 1076.45 4962.6 1151.45
P5.1/UCB1SIMO/UCB1SDA 46 4887.6 1212.05 4962.6 1287.05
P5.2/UCB1SOMI/UCB1SCL 47 4887.6 1352.15 4962.6 1427.15
P5.3/UCB1CLK/UCA1STE 48 4887.6 1492.25 4962.6 1567.25
P5.4/MCLK 49 4887.6 1627.85 4962.6 1702.85
P5.5/SMCLK 50 4887.6 2533.55 4962.6 2608.55
P5.6/ACLK 51 4887.6 2669.15 4962.6 2744.15
P5.7/TBOUTH/SVSOUT 52 4887.6 2804.75 4962.6 2879.75
DVCC2 53 4884.35 2953.25 4959.35 3028.25
DVSS2 54 4887.6 3060.45 4962.6 3135.45
P7.0 55 4887.6 3153.45 4962.6 3228.45
P7.1 56 4887.6 3289.05 4962.6 3364.05
P7.2 57 4887.6 3424.65 4962.6 3499.65
P7.3 58 4887.6 3560.25 4962.6 3635.25
P7.4 59 4887.6 3700.35 4962.6 3775.35
P7.5 60 4887.6 3840.45 4962.6 3915.45
P7.6 61 4887.6 3997.05 4962.6 4072.05
P7.7 62 4237.65 4887.6 4312.65 4962.6
P8.0 63 4102.05 4887.6 4177.05 4962.6
P8.1 64 3966.45 4887.6 4041.45 4962.6
P8.2 65 3830.85 4887.6 3905.85 4962.6
P8.3 66 3547.7 4887.6 3622.7 4962.6
P8.4 67 3412.1 4887.6 3487.1 4962.6
P8.5 68 3276.5 4887.6 3351.5 4962.6
P8.6/XT2OUT 69 3140.9 4887.6 3215.9 4962.6
P8.7/XT2IN 70 2992.85 4887.6 3067.85 4962.6
TDO/TDI 71 2844.6 4887.6 2919.6 4962.6
TDI/TCLK 72 2448 4887.6 2523 4962.6
TMS 73 2152.25 4887.6 2227.25 4962.6
TCK 74 1568.55 4887.6 1643.55 4962.6
RST/NMI 75 1431.85 4887.6 1506.85 4962.6
P6.0/A0 76 1230.75 4887.6 1305.75 4962.6
P6.1/A1 77 1077.9 4887.6 1152.9 4962.6
P6.2/A2 78 923.95 4887.6 998.95 4962.6
AVSS 79 821.05 4887.95 896.05 4962.95
AVSS 80 674.95 4887.6 749.95 4962.6
DVSS1 81 499.2 4887.6 574.2 4962.6
AVCC 82 337.85 4884.35 412.85 4959.35