SLASF88C October   2023  – September 2025 MSPM0G3505-Q1 , MSPM0G3506-Q1 , MSPM0G3507-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
        1. 7.6.1.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 SYSOSC Typical Frequency Accuracy
        1. 7.9.2.1 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 DAC
      1. 7.17.1 DAC_Supply Specifications
      2. 7.17.2 DAC Output Specifications
      3. 7.17.3 DAC Dynamic Specifications
      4. 7.17.4 DAC Linearity Specifications
      5. 7.17.5 DAC Timing Specifications
    18. 7.18 GPAMP
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
    19. 7.19 OPA
      1. 7.19.1 Electrical Characteristics
      2. 7.19.2 Switching Characteristics
      3. 7.19.3 PGA Mode
    20. 7.20 I2C
      1. 7.20.1 I2C Characteristics
      2. 7.20.2 I2C Filter
        1. 7.20.2.1 I2C Timing Diagram
    21. 7.21 SPI
      1. 7.21.1 SPI
      2. 7.21.2 SPI Timing Diagram
    22. 7.22 UART
    23. 7.23 TIMx
    24. 7.24 TRNG
      1. 7.24.1 TRNG Electrical Characteristics
      2. 7.24.2 TRNG Switching Characteristics
    25. 7.25 Emulation and Debug
      1. 7.25.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G350x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 MATHACL
    23. 8.23 UART
    24. 8.24 I2C
    25. 8.25 SPI
    26. 8.26 CAN-FD
    27. 8.27 WWDT
    28. 8.28 RTC
    29. 8.29 Timers (TIMx)
    30. 8.30 Device Analog Connections
    31. 8.31 Input/Output Diagrams
    32. 8.32 Serial Wire Debug Interface
    33. 8.33 Bootstrap Loader (BSL)
    34. 8.34 Device Factory Constants
    35. 8.35 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • PM|64
  • RGZ|48
  • RHB|32
  • DGS|32
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Core
    • Arm® 32-bit Cortex®-M0+ CPU with memory protection unit, frequency up to 80MHz
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 system design
    • Systematic capability up to ASIL B
    • Hardware integrity up to ASIL B
  • Safety-related certification
  • Operating characteristics
    • Extended temperature: –40°C up to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 128KB of flash memory with error correction code (ECC)
    • Up to 32KB of SRAM with hardware parity
  • High-performance analog peripherals
    • Two simultaneous sampling 12-bit 4Msps analog-to-digital converters (ADCs) with up to 17 external channels
      • 14-bit effective resolution at 250ksps with hardware averaging
    • One 12-bit 1Msps digital-to-analog converter with integrated output buffer (DAC)
    • Two zero-drift zero-crossover chopper op-amps (OPA)
      • 0.5µV/°C drift with chopping
      • Integrated programmable gain stage, up to 32x
    • One general-purpose amplifier (GPAMP)
    • Three high-speed comparators (COMP) with 8-bit reference DACs
      • 32ns propagation delay in high-speed mode
      • Support low-power mode operation down to 1µA
    • Programmable analog connections between ADC, OPAs, GPAMP, COMP and DAC
    • Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
    • Integrated temperature sensor
  • Optimized low-power modes
    • RUN: 101µA/MHz (CoreMark)
    • SLEEP: 40µA/MHz
    • STOP: 190µA at 4MHz
    • STANDBY: 1.5µA with 32KHz LFXT, RTC with SRAM, CPU state, and registers retained
    • SHUTDOWN: 80nA with IO retained and IO wake-up capability
  • Intelligent digital peripherals
    • 7-channel DMA controller
    • Math accelerator supports DIV, SQRT, MAC and TRIG computations
    • Seven timers supporting up to 22 PWM channels
      • One 16-bit general-purpose timer supports QEI
      • Two 16-bit general-purpose timers support low-power operation in STANDBY mode
      • One 32-bit general-purpose timer
      • Two 16-bit advanced timers with deadband support and complementary outputs up to 12 PWM channels
    • Two window-watchdog timers (WWDT)
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces
    • Four UART interfaces
      • One supports LIN, IrDA, DALI, Smart Card, Manchester
      • Three support low-power operation in STANDBY mode
    • Two I2C interfaces supporting FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode

    • Two SPIs, one SPI supports up to 32Mbits/s

    • One Controller Area Network (CAN) interface supports CAN 2.0 A or B and CAN-FD
  • Clock system
    • Internal 4MHz to 32MHz oscillator (SYSOSC) with up to ±1.2% accuracy (SYSOSC)
    • Phase-locked loop (PLL) up to 80MHz
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 4MHz to 48MHz crystal oscillator (HFXT)
    • External 32kHz crystal oscillator(LFXT)
    • External clock input
  • Data integrity and encryption
    • Cyclic redundancy checker (CRC-16, CRC-32)
    • True random number generator (TRNG)
    • AES encryption with 128-bit or 256-bit key
  • Flexible I/O features
    • Up to 60 GPIOs
      • Two 5V-tolerant open drain IOs
      • Two high-drive IOs with 20mA drive strength
      • Up to 5 high speed IOs
  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 64-pin LQFP (PM) (0.5mm pitch)
    • 48-pin LQFP (PT) (0.5mm pitch)
    • 48-pin VQFN (RGZ) (0.5mm pitch)
    • 32-pin VQFN (RHB) (0.5mm pitch)
    • 32-pin VSSOP (32DGS) (0.5mm pitch)
    • 28-pin VSSOP (28DGS) (0.5mm pitch)
  • Family members (also see Device Comparison)
    • MSPM0G3505: 32KB flash, 16KB RAM
    • MSPM0G3506: 64KB flash, 32KB RAM
    • MSPM0G3507: 128KB flash, 32KB RAM
  • Development kits and software (also see Tools and Software)
  • Automotive qualification
    • AEC-Q100 Grade 1
    • 32- and 48-pin QFN with wettable flanks option