SLASF88B October   2023  – May 2024 MSPM0G3507-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
        1. 7.6.1.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 SYSOSC Typical Frequency Accuracy
        1. 7.9.2.1 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 DAC
      1. 7.17.1 DAC_Supply Specifications
      2. 7.17.2 DAC Output Specifications
      3. 7.17.3 DAC Dynamic Specifications
      4. 7.17.4 DAC Linearity Specifications
      5. 7.17.5 DAC Timing Specifications
    18. 7.18 GPAMP
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
    19. 7.19 OPA
      1. 7.19.1 Electrical Characteristics
      2. 7.19.2 Switching Characteristics
      3. 7.19.3 PGA Mode
    20. 7.20 I2C
      1. 7.20.1 I2C Characteristics
      2. 7.20.2 I2C Filter
        1. 7.20.2.1 I2C Timing Diagram
    21. 7.21 SPI
      1. 7.21.1 SPI
      2. 7.21.2 SPI Timing Diagram
    22. 7.22 UART
    23. 7.23 TIMx
    24. 7.24 TRNG
      1. 7.24.1 TRNG Electrical Characteristics
      2. 7.24.2 TRNG Switching Characteristics
    25. 7.25 Emulation and Debug
      1. 7.25.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G350x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 MATHACL
    23. 8.23 UART
    24. 8.24 I2C
    25. 8.25 SPI
    26. 8.26 CAN-FD
    27. 8.27 WWDT
    28. 8.28 RTC
    29. 8.29 Timers (TIMx)
    30. 8.30 Device Analog Connections
    31. 8.31 Input/Output Diagrams
    32. 8.32 Serial Wire Debug Interface
    33. 8.33 Bootstrap Loader (BSL)
    34. 8.34 Device Factory Constants
    35. 8.35 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • PM|64
  • RGZ|48
  • RHB|32
  • RGE|24
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.19.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V
RRI = 0x1 -0.1 VDD-0.3
VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV
Iq Quiescent current, per op-amp IO= 0mA, RRI = 0x0 GBW = 0x0 94 µA
GBW = 0x1 319
IO= 0mA, RRI = 0x1 GBW = 0x0 116 134
GBW = 0x1 401 500
IBCS Burn-out current source current  2 µA
GBW Gain-bandwidth product Noninverting, unity gain,CL = 40pF GBW = 0x0 1.5 MHz
GBW = 0x1 6
VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV
CHOP = 0x1 or 0x2 ±0.3
Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5
CHOP = 0x1 or 0x2 ±0.1 ±0.5
dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 8.5 µV/°C
GBW = 0x1 6
CHOP = 0x1 or 0x2 0.5
PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB
CHOP = 0x1 or 0x2 74 86
Ibias  Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±50 pA
Ibias (PM Package) Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 125°C ±0.35 ±400 nA
Ibias (All packages except PM) Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 125°C ±0.35 ±100 nA
Ibias  Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA
Ibias (PM Package) Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 125°C ±0.4 ±400 nA
Ibias (All packages except PM) Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 125°C ±0.4 ±104 nA
CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1V
RRI = 0x1: 0V<VCM<VDD-0.3V		 CHOP = 0x0 89 dB
CHOP = 0x1 or 0x2 73 102
en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz
f = 10kHz 88
Integrated voltage noise, input referred f = 0.1Hz to 10Hz, GBW = 0x0, Noninverting, unity gain CHOP = 0x0 75 µVpp
CHOP = 0x1 or 0x2 2
Integrated voltage noise, output referred f = 0.1Hz to 10MHz, GBW = 0x0, CHOP = 0x0, Noninverting, unity gain 1.5 mVpp
Rin Input resistance (1) 2.6 kΩ
Cin Input capacitance Common mode 3 pF
AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB
PM phase margin CL = 40pF GBW = 0x0 57 degree
GBW = 0x1 50
SR Slew rate Noninverting, unity gain, CL = 40pF GBW = 0x0 1.3 V/µs
GBW = 0x1 4.9
THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 %
Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004
ILoad Output load current GBW = 0x0 ±9 mA
GBW = 0x1 ±30
CLoad Output load capacitance 40 pF
(1) Rin here means the input resistance of mux in OPA.