SLVSJB5 November 2025 MSPM0G5187
ADVANCE INFORMATION
Table 8-4 summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
|
MEMORY REGION |
SUBREGION |
MSPM0G5187 |
|---|---|---|
|
Code (Flash Bank 0) |
MAIN ECC Corrected |
64KB |
| 0x0000.0000 to 0x0000.FFFF | ||
|
MAIN ECC Uncorrected |
0x0040.0000 to 0x0040.FFFF | |
|
Flash ECC Code |
0x0080.0000 to 0x0080.FFFF | |
|
Code (Flash Bank 1) |
MAIN ECC Corrected |
64KB |
| 0x0001.0000 to 0x0001.FFFF | ||
|
MAIN ECC Uncorrected |
0x0041.0000 to 0x0001.FFFF | |
|
Flash ECC Code |
0x0081.0000 to 0x0001.FFFF | |
|
Data Flash Bank |
Data Flash ECC Corrected |
8KB |
| 0x41D0.0000 to 0x41D0.1FFF | ||
|
Data Flash Unchecked |
0x41E0.0000 to 0x41E0.1FFF | |
|
Data Flash ECC Code |
0x41F0.0000 to 0x41F0.1FFF | |
|
SRAM (SRAM) |
SRAM ECC Corrected |
32KB |
| 0x2000.0000 to 0x2000.7FFF | ||
|
SRAM Parity Checked |
0x2010.0000 to 0x2010.7FFF | |
|
SRAM Unchecked |
0x2020.0000 to 0x2020.7FFF | |
|
SRAM ECC/Parity Code |
0x2030.0000 to 0x2030.7FFF | |
|
Peripheral |
Peripherals |
0x4000.0000 to 0x40FF.FFFF |
|
NONMAIN Corrected |
1KB | |
| 0x41C0.0000 to 0x41C0.03FF | ||
|
NONMAIN Uncorrected |
0x41C1.0000 to 0x41C1.03FF | |
|
NONMAIN ECC Code |
0x41C2.0000 to 0x41C2.03FF | |
|
FACTORY Corrected |
512Bytes | |
|
0x41C4.0000 to 0x41C4.01FF |
||
|
FACTORY Uncorrected |
0x41C5.0000 to 0x41C5.01FF | |
|
FACTORY ECC code |
0x41C6.0000 to 0x41C6.01FF | |
|
Subsystem |
0x6000.0000 to 0x7FFF.FFFF | |
|
System PPB |
0xE000.0000 to 0xE00F.FFFF | |