SLLSEK1B July 2014 – March 2018 ONET2804T
The voltage drop across the regulated photodiode FET is monitored by the bias and RSSI control circuit block in the case where a PIN diode is biased using the FILTER pins.
If the DC input current exceeds a certain level then it is partially cancelled by means of a controlled current source. This keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of the complete amplifier.
Finally this circuit block senses the current through the FILTER FET and generates a mirrored current that is proportional to the input signal strength. The mirrored currents are available at the RSSI outputs and can be sunk to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSI pad does not exceed VCC - 0.65 V.