SBOS642C March 2013 – January 2020 OPA188
PRODUCTION DATA.
| DESCRIPTION | FIGURE |
|---|---|
| Offset Voltage Production Distribution | Figure 1 |
| Offset Voltage Drift Distribution | Figure 2 |
| Offset Voltage vs Temperature | Figure 3 |
| Offset Voltage vs Common-Mode Voltage | Figure 4, Figure 5 |
| Offset Voltage vs Power Supply | Figure 6 |
| Open-Loop Gain and Phase vs Frequency | Figure 7 |
| Closed-Loop Gain vs Frequency | Figure 8 |
| IB and IOS vs Common-Mode Voltage | Figure 9 |
| Input Bias Current vs Temperature | Figure 10 |
| Output Voltage Swing vs Output Current (Maximum Supply) | Figure 11 |
| CMRR and PSRR vs Frequency (Referred-to-Input) | Figure 12 |
| CMRR vs Temperature | Figure 13, Figure 14 |
| PSRR vs Temperature | Figure 15 |
| 0.1-Hz to 10-Hz Noise | Figure 16 |
| Input Voltage Noise Spectral Density vs Frequency | Figure 17 |
| THD+N Ratio vs Frequency | Figure 18 |
| THD+N vs Output Amplitude | Figure 19 |
| Quiescent Current vs Supply Voltage | Figure 20 |
| Quiescent Current vs Temperature | Figure 21 |
| Open-Loop Gain vs Temperature | Figure 22 |
| Open-Loop Output Impedance vs Frequency | Figure 23 |
| Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) | Figure 24, Figure 25 |
| No Phase Reversal | Figure 26 |
| Positive Overload Recovery | Figure 27 |
| Negative Overload Recovery | Figure 28 |
| Small-Signal Step Response (100 mV) | Figure 29, Figure 30 |
| Large-Signal Step Response | Figure 31, Figure 32 |
| Large-Signal Settling Time (10-V Positive Step) | Figure 33 |
| Large-Signal Settling Time (10-V Negative Step) | Figure 34 |
| Short-Circuit Current vs Temperature | Figure 35 |
| Maximum Output Voltage vs Frequency | Figure 36 |
| EMIRR IN+ vs Frequency | Figure 37 |