SBOS936E November   2019  – August 2022 OPA182 , OPA2182 , OPA4182

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA182
    5. 7.5 Thermal Information: OPA2182
    6. 7.6 Thermal Information: OPA4182
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Phase-Reversal Protection
      2. 8.3.2 Input Bias Current Clock Feedthrough
      3. 8.3.3 EMI Rejection
      4. 8.3.4 Electrical Overstress
      5. 8.3.5 MUX-Friendly Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Strain Gauge Analog Linearization
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Rogowski Coil Integrator
      3. 9.2.3 System Examples
        1. 9.2.3.1 24-Bit, Delta-Sigma, Differential Load Cell or Strain Gauge Sensor Signal Conditioning
      4. 9.2.4 Programmable Power Supply
      5. 9.2.5 RTD Amplifier With Linearization
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-B4918EE0-1026-4770-A2DB-82E83EE0724D-low.gifFigure 6-1 OPA182 D (8-Pin SOIC) Package, Top View
GUID-46355D70-D691-43FE-8681-6AFF5C358503-low.gifFigure 6-2 OPA182 DBV (5-Pin SOT-23) Package, Top View
Table 6-1 Pin Functions: OPA182
PIN TYPE DESCRIPTION
NAME D (SOIC) DBV (SOT-23)
–IN 2 4 Input Inverting input
+IN 3 3 Input Noninverting input
NC 1, 5, 8 — — No internal connection; can be left floating.
OUT 6 1 Output Output channel
V– 4 2 Power Negative supply
V+ 7 5 Power Positive supply
GUID-1105425F-FF67-451D-AC89-4A929538AC10-low.gifFigure 6-3 D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 6-2 Pin Functions: OPA2182
PIN TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Inverting input channel A
+IN A 3 Input Noninverting input channel A
–IN B 6 Input Inverting input channel B
+IN B 5 Input Noninverting input channel B
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
V– 4 Power Negative supply
V+ 8 Power Positive supply
GUID-1177C77E-708E-4A56-BE62-C975F4A79194-low.gifFigure 6-4 D (14-Pin SOIC) and PW (14-Pin TSSOP, Preview) Packages, Top View
Table 6-3 Pin Functions: OPA4182
PIN TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Inverting input channel A
+IN A 3 Input Noninverting input channel A
–IN B 6 Input Inverting input channel B
+IN B 5 Input Noninverting input channel B
–IN C 9 Input Inverting input channel C
+IN C 10 Input Noninverting input channel C
–IN D 13 Input Inverting input channel D
+IN D 12 Input Noninverting input channel D
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
OUT C 8 Output Output channel C
OUT D 14 Output Output channel D
V– 11 Power Negative supply
V+ 4 Power Positive supply