SBOS789C August   2017  – February 2020 OPA2810


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Multichannel Sensor Interface
      2.      Harmonic Distortion vs Frequency
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: 10 V
    6. 7.6  Electrical Characteristics: 24 V
    7. 7.7  Electrical Characteristics: 5 V
    8. 7.8  Typical Characteristics: VS = 10 V
    9. 7.9  Typical Characteristics: VS = 24 V
    10. 7.10 Typical Characteristics: VS = 5 V
    11. 7.11 Typical Characteristics: ±2.375 V to ±12 V Split Supply
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OPA2810 Architecture
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 8.4.2 Single-Supply Operation (4.75 V to 27 V)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Selection of Feedback Resistors
      2. 9.1.2 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 9.2 Typical Applications
      1. 9.2.1 Transimpedance Amplifier
        1. Design Requirements
        2. Detailed Design Procedure
      2. 9.2.2 Multichannel Sensor Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

OPA2810 Architecture

The OPA2810 features a true high-impedance input stage including a JFET differential-input pair main stage and a CMOS differential-input auxiliary (Aux) stage operational within 2.5 V of the positive supply voltage. The bias current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The Functional Block Diagram section shows a block diagram representation for the input stage of the OPA2810.

The amplifier exhibits superior performance for high-speed signals (distortion, noise and input offset voltage) while the Aux stage enables rail-to-rail inputs and prevents phase reversal. The OPA2810 also includes input clamps which enable maximum input differential voltage of upto 7 V (lower of 7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with multiplexers and processing of signals with fast transients. The input bias currents are also clamped to maximum 300 µA, as Figure 57 shows, which does not load the previous driver stage or require current-limiting resistors (except limiting current through the input ESD diodes when input common-mode voltages are greater than the supply voltages). This also enables the use of one of the channels as a comparator in systems which require an amplifier and a comparator for signal-gain and fault-detection, respectively. For the lowest offset, distortion and noise performance, limit the common-mode input voltage to the main JFET-input stage (greater than 2.5 V away from the positive supply).

The OPA2810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in Figure 16 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a 10–V supply. The outputs are short-circuit protected with the limits of Figure 17.

An amplifier phase margin reduces and it becomes unstable when driving a capacitive load (CL) at the output, as Figure 62 shows. Use of a series resistor (RS) between the amplifier output and load capacitance introduces a zero which cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function. The OPA2810 drives capacitive loads of up to 35 pF without causing instability. It is recommended to use a series resistor for larger load capacitance values, as Figure 4 shows for OPA2810 configured as a unity-gain buffer.

OPA2810 Driving_Capacitive_Loads.gifFigure 62. OPA2810 Driving Capacitive Load