SBOSAB2A february   2023  – july 2023 OPA2863-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = ±5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: VS = 3 V to 10 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. 8.3.2.1 Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Sensing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Front-End Gain and Filtering
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Typical Characteristics: VS = 3 V to 10 V

at G = 1 V/V, VOUT = 2 VPP, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to mid-supply, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

GUID-20230628-SS0I-2NVT-J4LF-K847XPRTJSPK-low.svg
VOUT = 20 mVPP
Figure 7-34 Frequency Response vs Supply Voltage
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Figure 7-36 Input Voltage Noise Density vs Frequency
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Figure 7-38 Common-Mode Rejection Ratio vs Frequency
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Figure 7-40 Open-Loop Output Impedance vs Frequency
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VOUT = 2 VPP
Figure 7-42 Harmonic Distortion vs Supply Voltage
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VOUT = 1 VPP
Figure 7-35 Frequency Response vs Supply Voltage
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Figure 7-37 Input Current Noise Density vs Frequency
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Figure 7-39 Power Supply Rejection Ratio vs Frequency
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Small-signal response
Figure 7-41 Open-Loop Gain and Phase vs Frequency
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Figure 7-43 Crosstalk vs Frequency