SLOS896B December   2014  – January 2017 OPA2314-Q1 , OPA314-Q1 , OPA4314-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA314-Q1
    5. 6.5 Thermal Information: OPA2314-Q1
    6. 6.6 Thermal Information: OPA4314-Q1
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Input and ESD Protection
      4. 7.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5 EMI Susceptibility and Input Filtering
      6. 7.3.6 Rail-to-Rail Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Configurations
      2. 8.1.2 Capacitive Load and Stability
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Amplifier Selection
        2. 8.2.2.2 Passive Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage 7 V
Voltage(2) Signal input terminals (V–) – 0.5 (V+) + 0.5 V
Current(2) Signal input terminals ±10 mA
Output short-circuit(3) Continuous mA
Operating temperature, TA –40 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage 1.8 (±0.9) 5.5 (±2.75) V
TA Ambient operating temperature –40 125 °C

6.4 Thermal Information: OPA314-Q1

THERMAL METRIC(1) OPA314-Q1 UNIT
DBV (SOT-23)
5 PINS
RθJA Junction-to-ambient thermal resistance(2) 221.7 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 144.7 °C/W
RθJB Junction-to-board thermal resistance(4) 49.7 °C/W
ψJT Junction-to-top characterization parameter(5) 26.1 °C/W
ψJB Junction-to-board characterization parameter(6) 49 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Thermal Information: OPA2314-Q1

THERMAL METRIC(1) OPA2314-Q1 UNIT
DGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance(2) 138.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 89.5 °C/W
RθJB Junction-to-board thermal resistance(4) 78.6 °C/W
ψJT Junction-to-top characterization parameter(5) 29.9 °C/W
ψJB Junction-to-board characterization parameter(6) 78.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.6 Thermal Information: OPA4314-Q1

THERMAL METRIC(1) OPA4314-Q1 UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance(2) 121 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 49.4 °C/W
RθJB Junction-to-board thermal resistance(4) 62.8 °C/W
ψJT Junction-to-top characterization parameter(5) 5.9 °C/W
ψJB Junction-to-board characterization parameter(6) 62.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.7 Electrical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, VS = 1.8 V to 5.5 V, unless otherwise noted. The phrase overtemperature refers to values over the specified temperature range of TA = –40°C to 125°C.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = (VS+) – 1.3 V 0.5 2.5 mV
dVOS/dT Input offset voltage vs temperature 1 μV/°C
PSRR vs power supply VCM = (VS+) – 1.3 V 78 92 dB
Input offset voltage overtemperature 74 dB
Channel separation, DC At DC 10 µV/V
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 1.8 V to 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 75 96 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2) 66 80 dB
Common-mode rejection ratio overtemperature VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 70 86 dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 73 90 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2) 60 dB
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±10 pA
Input bias current overtemperature ±600 pA
IOS Input offset current ±0.2 ±10 pA
Input offset current overtemperature ±600 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 5 μVPP
en Input voltage noise density f = 10 kHz 13 nV/√Hz
f = 1 kHz 14 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
INPUT CAPACITANCE
CIN Differential VS = 5 V 1 pF
Common-mode VS = 5 V 5 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 115 dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 100 128 dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ(2) 90 100 dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ(2) 94 110 dB
Open-loop voltage gain overtemperature VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 110 dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ 100 dB
Phase margin VS = 5 V, G = 1, RL = 10 kΩ 65 degrees
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 1.8 V, RL = 10 kΩ, CL = 10 pF 2.7 MHz
VS = 5 V, RL = 10 kΩ, CL = 10 pF 3 MHz
SR Slew rate (3) VS = 5 V, G = 1 1.5 V/μs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = 1 2.3 μs
To 0.01%, VS = 5 V, 2-V step , G = 1 3.1 μs
Overload recovery time VS = 5 V, VIN  × Gain > VS 5.2 μs
THD+N Total harmonic distortion + noise (4) VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ 0.001%
OUTPUT
VO Voltage output swing from supply rails VS = 1.8 V, RL = 10 kΩ 5 15 mV
VS = 5.5 V, RL = 10 kΩ 5 20 mV
VS = 1.8 V, RL = 2 kΩ 15 30 mV
VS = 5.5 V, RL = 2 kΩ 22 40 mV
Voltage output swing from supply rails overtemperature VS = 5.5 V, RL = 10 kΩ 30 mV
VS = 5.5 V, RL = 2 kΩ 60 mV
ISC Short-circuit current VS = 5 V ±20 mA
RO Open-loop output impedance VS = 5.5 V, f = 100 Hz 570 Ω
POWER SUPPLY
VS Specified voltage range 1.8 5.5 V
IQ Quiescent current per amplifier VS = 1.8 V, IO = 0 mA 130 180 µA
VS = 5 V, IO = 0 mA 150 190 µA
Quiescent current per amplifier overtemperature VS = 5 V, IO = 0 mA 220 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 44 µs
TEMPERATURE
Specified range –40 125 °C
Operating range –40 150 °C
Storage range –65 150 °C
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.
(3) Signifies the slower value of the positive or negative slew rate.
(4) Third-order filter; bandwidth = 80 kHz at –3 dB.

6.8 Typical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted

Table 1. Characteristic Performance Measurements

TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Open-Loop Gain vs Temperature Figure 2
Quiescent Current vs Supply Voltage Figure 3
Quiescent Current vs Temperature Figure 4
Offset Voltage Production Distribution Figure 5
Offset Voltage Drift Distribution Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 7
Offset Voltage vs Temperature Figure 8
CMRR and PSRR vs Frequency (RTI) Figure 9
CMRR and PSRR vs Temperature Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V) Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V) Figure 13
Input Bias and Offset Current vs Temperature Figure 14
Open-Loop Output Impedance vs Frequency Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage Figure 16
Output Voltage Swing vs Output Current (over Temperature) Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V) Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V) Figure 19
Small-Signal Overshoot vs Load Capacitance Figure 20
Small-Signal Step Response, Noninverting (1.8 V) Figure 21
Small-Signal Step Response, Noninverting ( 5.5 V) Figure 22
Large-Signal Step Response, Noninverting (1.8 V) Figure 23
Large-Signal Step Response, Noninverting ( 5.5 V) Figure 24
Positive Overload Recovery Figure 25
Negative Overload Recovery Figure 26
No Phase Reversal Figure 27
Channel Separation vs Frequency (Dual) Figure 28
THD+N vs Amplitude (G = 1, 2 kΩ, 10 kΩ) Figure 29
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ) Figure 30
THD+N vs Frequency (0.5 VRMS, G = 1, 2 kΩ, 10 kΩ) Figure 31
EMIRR Figure 32
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_open_loop_gain_phase_fqcy_slos896.gif
RL = 10 kΩ / 10 pF VS = ±2.5 V
Figure 1. Open-loop Gain and Phase vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_iq_vsupply_slos896.gif
Figure 3. Quiescent Current vs Supply
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_histo_voffset_slos896.gif
Figure 5. Offset Voltage Production Distribution
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_vos_vcm_slos896.gif
Typical units VS = ±2.75 V
Figure 7. Offset Voltage vs Common-Mode Voltage
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_cmrr_psrr_fqcy_slos896.gif
VS = ±2.75 V
Figure 9. CMRR and PSRR vs Frequency (Referred-to-Input)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_input_volt_noise_bos563.gif
Figure 11. 0.1-Hz to 10-Hz Input Voltage Noise
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_vnoise_vcm_slos896.gif
f = 1 kHz VS = ±2.75 V
Figure 13. Voltage Noise vs Common-Mode Voltage
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_open_loop_output_imped_fqcy_slos896.gif
Figure 15. Open-Loop Output Impedance vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_vout_swing_iout_slos896.gif
VS = ±2.75 V
Figure 17. Output Voltage Swing vs Output Current (Overtemperature)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_closed_loop_gain_fqcy_55v_slos896.gif
VS = 5.5 V
Figure 19. Closed-Loop Gain vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_sm_sig_step_09V_slos896.gif
RF = 10 kΩ VS = ±0.9 V G = 1 V/V
Figure 21. Small-Signal Pulse Response (Noninverting)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_lg_sig_step_09V_slos896.gif
RL = 10 kΩ VS = ±0.9 V G = 1 V/V
Figure 23. Large-Signal Pulse Response (Noninverting)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_ovrload_recover_pos_slos896.gif
Figure 25. Positive Overload Recovery
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_anti_phase_reversal_slos896.gif
Figure 27. No Phase Reversal
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_thdn_out_ampl_g1_slos896.gif
f = 1 kHz VS = ±2.5 V G = 1 V/V
BW = 80 kHz
Figure 29. THD+N vs Output Amplitude (G = 1 V/V)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_thdn_fqcy_g1_slos896.gif
VOUT = 0.5 VRMS VS = ±2.5 V G = 1 V/V
BW = 80 kHz
Figure 31. THD+N vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_open_loop_gain_temp_slos896.gif
Figure 2. Open-Loop Gain vs Temperature
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_iq_temp_slos896.gif
Figure 4. Quiescent Current vs Temperature
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_histo_voffset_drift_slos896.gif
Figure 6. Offset Voltage Drift Distribution
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_vos_temp_slos896.gif
Typical units VS = ±2.75 V
Figure 8. Offset Voltage vs Temperature
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_cmrr_psrr_temp_slos896.gif
Figure 10. CMRR and PSRR vs Temperature
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_vin_spec_density_fqcy_slos896.gif
Figure 12. Input Voltage Noise Spectral Density vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_input_bias_temp_slos896.gif
Figure 14. Input Bias and Offset Current vs Temperature
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_max_vout_fqcy_slos896.gif
RL = 10 kΩ CL = 10 pF
Figure 16. Maximum Output Voltage vs Frequency and Supply Voltage
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_closed_loop_gain_fqcy_18v_slos896.gif
VS = 1.8 V
Figure 18. Closed-Loop Gain vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_sm_sig_ovrsht_cap_load_slos896.gif
RL = 10 kΩ VS = ±2.75 V G = 1 V/V
Figure 20. Small-Signal Overshoot vs Load Capacitance
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_sm_sig_step_275V_slos896.gif
RF = 10 kΩ VS = ±2.75 V G = 1 V/V
Figure 22. Small-Signal Pulse Response (Inverting)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_lg_sig_step_275V_slos896.gif
RL = 10 kΩ VS = ±2.75 V G = 1 V/V
Figure 24. Large-Signal Pulse Response (Inverting)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_ovrload_recover_neg_slos896.gif
Figure 26. Negative Overload Recovery
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_chan_separat_fqcy_slos896.gif
VS = ±2.75 V
Figure 28. Channel Separation vs Frequency
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_thdn_out_ampl_g-1_slos896.gif
f = 1 kHz VS = ±2.5 V G = –1 V/V
BW = 80 kHz
Figure 30. THD+N vs Output Amplitude (G = –1 V/V)
OPA314-Q1 OPA2314-Q1 OPA4314-Q1 tc_emirr_2314_slos896.gif
PRF = –10 dBm VS = ±2.5 V VCM = 0 V
Figure 32. Electromagnetic Interference Rejection Ratio Referred To Noninverting Input (EMIRR IN+) vs Frequency