SBOS926G January   2021  – April 2024 OPA2392 , OPA392

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information - OPA392
    5. 6.5 Thermal Information - OPA2392
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Operating Voltage
      2. 7.3.2 Low Input Bias Current
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • YBJ|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

at TA = 25°C, VS = 1.7 V to 5.5 V (single-supply) or VS = ±0.85 V to ±2.75 V (dual-supply), RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5.0 V ±1 ±10 μV
OPA2392D ±1 ±20
OPA392YBJ, OPA2392YBJ ±1 ±25
VS = 5.0 V, 
VCM = (V+) – 200 mV		 ±2 ±30
OPA2392YBJ ±2 ±85
VS = 5.0 V, 
TA = –40°C to +125°C(1)		 ±100
VCM = V–, 
TA = –40°C to +125°C(1)		 ±125
dVOS/dT Input offset voltage drift VS = 5.0 V TA = 0°C to 85°C ±0.16 μV/°C
TA = –40°C to +125°C(1) ±0.6
VCM = 5.0 V, 
TA = –40°C to +125°C(1)		 ±0.18 ±0.9
PSRR Power supply rejection ratio VCM = V– ±30 μV/V
TA = –40°C to +125°C(1) ±80
INPUT BIAS CURRENT
IB Input bias current(1) ±0.01 ±0.8 pA
TA = –40°C to +85°C ±5
TA = –40°C to +125°C ±30
IOS Input offset current(1) ±0.01 ±0.8 pA
TA = –40°C to +85°C ±5
TA = –40°C to +125°C ±30
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 2.0 μVPP
VCM = (V+) – 0.3   3.2
eN Input voltage noise density f = 10 Hz   42   nV/√Hz
VCM = (V+) – 0.3 80
f = 1 kHz 6.5
VCM = (V+) – 0.3   10.4  
f = 10 kHz   4.4
VCM = (V+) – 0.3 5.8
iN Input current noise density f = 1 kHz OPA392DBV   70   fA/√Hz
OPA392YBJ, OPA2392 25
INPUT VOLTAGE
VCM Common-mode voltage range V– V+ V
CMRR Common-mode rejection ratio (V–) < VCM < (V+) – 1.5 V 75 120 dB
TA = –40°C to +125°C 113
(V–) < VCM < (V+), 
TA = –40°C to +125°C(1)		 66 97
VS = 5.5 V 88 111
INPUT CAPACITANCE
ZID Differential 1013 || 2.8 Ω || pF
ZICM Common-mode 1013 || 3.5 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 5.5 V (V–) + 50 mV < VOUT <
(V+) – 50 mV		 115 132 dB
(V–) + 100 mV < VO <
(V+) – 100 mV, RL = 2 kΩ		 110 128
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ, 
TA = –40°C to +125°C(1)		 100
VS = 1.7 V (V–) + 50 mV < VOUT <
(V+) – 50 mV, 
VCM = (V+) – 1.15 V		 106 124
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ, 
VCM = (V+) – 1.15 V		 106 124
(V–) + 100 mV < VOUT <
(V+) – 100 mV, RL = 2 kΩ, 
VCM = (V+) – 1.15 V, 
TA = –40°C to +125°C(1)		 100
FREQUENCY RESPONSE
GBW Gain-bandwidth product AV = 1000 V/V 13 MHz
SR Slew rate 4-V step, gain = +1 falling 4.5 V/μs
rising 3.5
Phase margin CL = 100 pF 45 °
tS Settling time To 0.1%, 2-V step, gain = +1 0.75 μs
To 0.01%, 2-V step, gain = +1 1
Overload recovery time VIN × gain > VS 0.45 μs
THD+N Total harmonic distortion + noise VOUT = 1 VRMS, gain = +1, f = 1 kHz,
VCM = (V–) + 1.5 V		 –112 dB
0.00025 %
OUTPUT
Voltage output swing from both rails VS = 1.7 V 20 mV
RL = 2 kΩ 30
VS = 5.5 V 20
RL = 2 kΩ 35
ISC Short-circuit current Sinking, VS = 5.5 V –55 mA
Sourcing, VS = 5.5 V 65
RO Open-loop output impedance f = 1 MHz 120 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 mA 1.22 1.4 mA
TA = –40°C to +125°C(1) 1.5
SHUTDOWN (OPA392YBJ, OPA2392YBJ and OPA4392RTE Only)
IQSD Quiescent current per amplifier All amplifiers disabled, EN = V– 6 µA
VIH High-level input voltage Amplifier enabled (V+) – 0.5 V
VIL Low-level input voltage Amplifier disabled (V–) + 0.5 V
tON Amplifier enable time G = 1, VOUT = 0.9 × VS/2, two amplifiers enabled 9.5 µs
tOFF Amplifier disable time G = 1, VOUT = 0.1 × VS/2, two amplifiers disabled 7.8 µs
EN pin input leakage current VIH = V+ 0.02 µA
VIL = V– 1
(1) Specification established from device population bench system measurements across multiple lots.