SBOS981J October   2019  – April 2021 OPA2607 , OPA607


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
      2. 8.4.2 Power Down Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      5. 9.2.5 Ultrasonic Flow Meters
        1. Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input and ESD Protection

When the primary design goal is a linear amplifier with high CMRR, do not exceed the op amp input common-mode voltage range (VCM). This CMRR is used to set the common-mode input range specifications in Section 7.5. The typical VCM specifications for the OPAx607 devices are from the negative rail to 1.1 V below the positive rail. Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V) and the input common-mode voltage can be analyzed at either input pin; the other input pin is assumed to be at the same potential. The voltage at VIN+ is easy to evaluate. In a noninverting configuration (Figure 8-1) the input signal, VIN+, must not exceed the VCM rating. However, in an inverting amplifier configuration, VIN+ must be connected to the voltage within VCM. The input signal applied at VIN- can be any voltage, such that the output voltage swings with a headroom of 10 mV from either of the supply rails.

The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For single 5-V supply, the linear input voltage range is 0 V to 3.9 V and with a 2.2-V supply this range is 0 V to 1.1 V. The headroom to each power-supply rail is the same in either case: 0 V and 1.1 V. A weak NMOS input pair from VIN+ to VIN+ – 1.1 V ensures that an output phase reversal issue does not occur when the VCM is violated.

GUID-FB892DCE-69D0-417D-A194-76D58AC26331-low.gifFigure 8-4 Internal ESD Structure

The OPAx607 devices also incorporate internal electrostatic discharge (ESD) protection circuits on all pins. For the input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provides input overdrive protection, as long as the current is limited with a series resistor to 10 mA, as stated in Section 7.1. Figure 8-1 shows a series input resistor can be added to the driven input to limit the input current.