SBOSA57A February   2021  – March 2021 OPA855-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings 
    2. 6.2 ESD Ratings 
    3. 6.3 Recommended Operating Conditions 
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 Wide Gain-Bandwidth Product
      4. 8.3.4 Slew Rate and Output Stage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Parameter Measurement Information

The various test setup configurations for the OPA855-Q1 are shown in Figure 7-1, Figure 7-2, and Figure 7-3. When configuring the OPA855-Q1 in a gain of +39.2 V/V, feedback resistor RF was set to 953 Ω.

Figure 6-1 shows 5-dB of peaking with the amplifier in an inverting configuration of –7 V/V with the amplifier configured as shown in Figure 7-2. The 50-Ω matched termination of this circuit configuration results in the amplifier being configured in a noise gain of 5.3 V/V, which is lower than the recommended +7 V/V.

GUID-C4200420-68AD-4210-9603-4D349529E704-low.gifFigure 7-1 Noninverting Configuration
GUID-2577CB9C-B389-4CE8-A856-CB77CBBD27BB-low.gifFigure 7-2 Inverting Configuration (Gain = –7 V/V)
GUID-0F648E9C-ADC7-42FE-B934-8CCF5B5DB7BE-low.gifFigure 7-3 Capacitive Load Driver Configuration