SBOS629B April   2018  – May 2025 OPA858

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 Wide Gain-Bandwidth Product
      4. 8.3.4 Slew Rate and Output Stage
      5. 8.3.5 Current Noise
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the OPA858 as a Transimpedance Amplifier
    2. 9.2 Typical Applications
      1. 9.2.1 TIA in an Optical Front-End System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • Y|0
  • DSG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 1.2 GHz C
LSBW Large-signal bandwidth VOUT = 2 VPP 600 MHz C
GBWP Gain-bandwidth product 5.5 GHz C
Bandwidth for 0.1-dB flatness 130 MHz C
SR Slew rate (10%–90%) VOUT = 2-V step 2000 V/µs C
tr Rise time VOUT = 100-mV step 0.3 ns C
tf Fall time VOUT = 100-mV step 0.3 ns C
Settling time to 0.1% VOUT = 2-V step 8 ns C
Settling time to 0.001% VOUT = 2-V step 3000 ns C
Overshoot or undershoot VOUT = 2-V step 7% C
Overdrive recovery 2x output overdrive (0.1% recovery) 200 ns C
HD2 Second-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 88 dBc C
f = 100 MHz, VOUT = 2 VPP 64
HD3 Third-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 86 dBc C
f = 100 MHz, VOUT = 2 VPP 68
en Input-referred voltage noise f = 1 MHz 2.5 nV/√Hz C
ZOUT Closed-loop output impedance f = 1 MHz 0.15 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain(2) 72 75 dB A
VOS Input offset voltage(2) TA = 25°C –5 ±0.8 5 mV A
ΔVOS/ΔT Input offset voltage drift TA = –40°C to +125°C ±2 µV/°C B
IBN, IBI Input bias current(2) TA = 25°C ±0.4 5 pA A
IBOS Input offset current(2) TA = 25°C ±0.01 5 pA A
CMRR Common-mode rejection ratio(2) VCM = ±0.5 V, referenced to midsupply 70 90 dB A
INPUT
Common-mode input resistance 1 GΩ C
CCM Common-mode input capacitance 0.62 pF C
Differential input resistance 1 GΩ C
CDIFF Differential input capacitance 0.2 pF C
VIH Common-mode input
voltage (high)(2)		 CMRR > 66 dB, VS+ = 3.3 V 1.7 1.9 V A
VIL Common-mode input
voltage (low)(2)		 CMRR > 66 dB, VS+ = 3.3 V 0 0.4 V A
VIH Common-mode input
voltage (high)(2)		 CMRR > 66 dB 3.4 3.6 V A
TA = –40°C to +125°C,
CMRR > 66 dB		 3.4 B
VIL Common-mode input
voltage (low)(2)		 CMRR > 66 dB 0 0.4 V A
TA = –40°C to +125°C,
CMRR > 66 dB		 0.35 B
OUTPUT
VOH Output voltage (high) TA = 25°C, VS+ = 3.3 V 2.3 2.4 V A
TA = 25°C 3.95 4.1 A
TA = –40°C to +125°C 3.9 B
VOL Output voltage (low) TA = 25°C, VS+ = 3.3 V 1.05 1.15 V A
TA = 25°C 1.05 1.15 A
TA = –40°C to +125°C 1.2 B
Linear output drive (sink and source)(2) RL = 10 Ω, AOL > 60 dB 65 80 mA A
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 60 dB		 64 B
ISC Output short-circuit current(2) 85 105 mA A
POWER SUPPLY
IQ Quiescent current VS+ = 5 V 18 20.5 24 mA A
VS+ = 3.3 V 17.5 20 23.5 A
VS+ = 5.25 V 18 21 24 A
TA = 125°C 24.5 B
TA = –40°C 18.5 B
PSRR+ Positive power-supply rejection ratio(2) 74 84 dB A
PSRR– Negative power-supply rejection ratio(2) 70 80 dB A
POWER DOWN
Disable voltage threshold Amplifier off when < this voltage 0.65 1 V A
Enable voltage threshold Amplifier on when > this voltage 1.5 1.8 V A
Power-down quiescent current 70 140 µA A
PD bias current 70 200 µA A
Turn-on time delay Time to VOUT = 90% of final value 13 ns C
Turn-off time delay 120 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2)
MIN and MAX limits do not apply for bare die.