SBAS989 April   2019 PCM1840

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Input Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear Phase Filters
            1. 7.3.7.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 7.3.7.2.2 Low-Latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.7.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.7.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.7.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.7.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 7.3.8 Dynamic Range Enhancer (DRE)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Active Mode

In the hardware shutdown state, when the SHDNZ pin goes high, the device starts the internal boot-up sequence and then enters into active mode in less than 20 ms (typical). Assert the SHDNZ pin high only when the IOVDD supply settles to a steady voltage level and all hardware control pins (MSZ, MD0, MD1, FMT0, and FMT1) are driven to the voltage level for the device desired mode of operation.

In active mode, when the audio clocks are available, the device powers up all the ADC channels and starts transmitting the data over the audio serial interface. If the clocks are stopped then the device auto powers down the ADC channels.