SBOS600F July   2018  – July 2026 REF20

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Solder Heat Shift
    2. 7.2 Long-Term Stability
    3. 7.3 Thermal Hysteresis
    4. 7.4 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VREF and VBIAS Tracking
      2. 8.3.2 Low Temperature Drift
      3. 8.3.3 Load Current
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Low-Side, Current-Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Shunt Resistor
          2. 9.2.1.2.2 Differential Amplifier
          3. 9.2.1.2.3 Voltage Reference
          4. 9.2.1.2.4 Results
        3. 9.2.1.3 Application Curves
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

9.4.1 Layout Guidelines

Figure 9-10 shows an example of a PCB layout for a data acquisition system using the REF2030. Some key considerations are:

  • Connect low-ESR, 0.1μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030.
  • Decouple other active devices in the system per the device specifications.
  • Use a solid ground plane to distribute heat and reduce electromagnetic interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.