SPRS947 June   2016 SM320C6748-HIREL

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
      1. 3.2.1  Device Reset, NMI and JTAG
      2. 3.2.2  High-Frequency Oscillator and PLL
      3. 3.2.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.2.4  DEEPSLEEP Power Control
      5. 3.2.5  External Memory Interface A (EMIFA)
      6. 3.2.6  DDR2/mDDR Controller
      7. 3.2.7  Serial Peripheral Interface Modules (SPI)
      8. 3.2.8  Programmable Real-Time Unit (PRU)
      9. 3.2.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.2.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.2.11 Boot
      12. 3.2.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.2.13 Inter-Integrated Circuit Modules (I2C0, I2C1)
      14. 3.2.14 Timers
      15. 3.2.15 Multichannel Audio Serial Ports (McASP)
      16. 3.2.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.2.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.2.18 Ethernet Media Access Controller (EMAC)
      19. 3.2.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.2.20 Liquid Crystal Display Controller (LCDC)
      21. 3.2.21 Serial ATA Controller (SATA)
      22. 3.2.22 Universal Host-Port Interface (UHPI)
      23. 3.2.23 Universal Parallel Port (uPP)
      24. 3.2.24 Video Port Interface (VPIF)
      25. 3.2.25 General Purpose Input Output
      26. 3.2.26 Reserved and No Connect
      27. 3.2.27 Supply and Ground
    3. 3.3 Pin Multiplexing
    4. 3.4 Connections for Unused Pins
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Power-On-Hours (POH) Limits
    4. 4.4 Recommended Operating Conditions
    5. 4.5 Electrical Characteristics
    6. 4.6 Thermal Data for GWT Package
    7. 4.7 Timing and Switching Characteristics
      1. 4.7.1 Timing Parameters and Information
        1. 4.7.1.1 Signal Transition Levels
      2. 4.7.2 Power Supply Sequencing
        1. 4.7.2.1 Power-On Sequence
        2. 4.7.2.2 Power-Off Sequence
      3. 4.7.3 Reset Timing
        1. 4.7.3.1 Reset Electrical Data/Timing
      4. 4.7.4 Clock Specifications
        1. 4.7.4.1 Crystal Oscillator or External Clock Input
        2. 4.7.4.2 Clock PLLs
          1. 4.7.4.2.1 PLL Device-Specific Information
          2. 4.7.4.2.2 Device Clock Generation
          3. 4.7.4.2.3 Dynamic Voltage and Frequency Scaling (DVFS)
      5. 4.7.5 Recommended Clock and Control Signal Transition Behavior
      6. 4.7.6 Peripherals
        1. 4.7.6.1  Power and Sleep Controller (PSC)
          1. 4.7.6.1.1 Power Domain and Module Topology
            1. 4.7.6.1.1.1 Power Domain States
            2. 4.7.6.1.1.2 Module States
        2. 4.7.6.2  Enhanced Direct Memory Access Controller (EDMA3)
          1. 4.7.6.2.1 EDMA3 Channel Synchronization Events
          2. 4.7.6.2.2 EDMA3 Peripheral Register Descriptions
        3. 4.7.6.3  External Memory Interface A (EMIFA)
          1. 4.7.6.3.1 EMIFA Asynchronous Memory Support
          2. 4.7.6.3.2 EMIFA Synchronous DRAM Memory Support
          3. 4.7.6.3.3 EMIFA SDRAM Loading Limitations
          4. 4.7.6.3.4 EMIFA Connection Examples
          5. 4.7.6.3.5 External Memory Interface Register Descriptions
          6. 4.7.6.3.6 EMIFA Electrical Data/Timing
        4. 4.7.6.4  DDR2/mDDR Memory Controller
          1. 4.7.6.4.1 DDR2/mDDR Memory Controller Electrical Data/Timing
          2. 4.7.6.4.2 DDR2/mDDR Memory Controller Register Description(s)
          3. 4.7.6.4.3 DDR2/mDDR Interface
            1. 4.7.6.4.3.1  DDR2/mDDR Interface Schematic
            2. 4.7.6.4.3.2  Compatible JEDEC DDR2/mDDR Devices
            3. 4.7.6.4.3.3  PCB Stackup
            4. 4.7.6.4.3.4  Placement
            5. 4.7.6.4.3.5  DDR2/mDDR Keep Out Region
            6. 4.7.6.4.3.6  Bulk Bypass Capacitors
            7. 4.7.6.4.3.7  High-Speed Bypass Capacitors
            8. 4.7.6.4.3.8  Net Classes
            9. 4.7.6.4.3.9  DDR2/mDDR Signal Termination
            10. 4.7.6.4.3.10 VREF Routing
            11. 4.7.6.4.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
            12. 4.7.6.4.3.12 DDR2/mDDR Boundary Scan Limitations
        5. 4.7.6.5  Memory Protection Units
        6. 4.7.6.6  MMC / SD / SDIO (MMCSD0, MMCSD1)
          1. 4.7.6.6.1 MMCSD Peripheral Description
          2. 4.7.6.6.2 MMCSD Peripheral Register Description(s)
          3. 4.7.6.6.3 MMC/SD Electrical Data/Timing
        7. 4.7.6.7  Serial ATA Controller (SATA)
          1. 4.7.6.7.1 SATA Register Descriptions
          2. 4.7.6.7.2 1. SATA Interface
            1. 4.7.6.7.2.1 SATA Interface Schematic
            2. 4.7.6.7.2.2 Compatible SATA Components and Modes
            3. 4.7.6.7.2.3 PCB Stackup Specifications
            4. 4.7.6.7.2.4 Routing Specifications
            5. 4.7.6.7.2.5 Coupling Capacitors
            6. 4.7.6.7.2.6 SATA Interface Clock Source requirements
          3. 4.7.6.7.3 SATA Unused Signal Configuration
        8. 4.7.6.8  Multichannel Audio Serial Port (McASP)
          1. 4.7.6.8.1 McASP Peripheral Registers Description(s)
          2. 4.7.6.8.2 McASP Electrical Data/Timing
            1. 4.7.6.8.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        9. 4.7.6.9  Multichannel Buffered Serial Port (McBSP)
          1. 4.7.6.9.1 McBSP Peripheral Register Description(s)
          2. 4.7.6.9.2 McBSP Electrical Data/Timing
            1. 4.7.6.9.2.1 Multichannel Buffered Serial Port (McBSP) Timing
        10. 4.7.6.10 Serial Peripheral Interface Ports (SPI0, SPI1)
          1. 4.7.6.10.1 SPI Peripheral Registers Description(s)
          2. 4.7.6.10.2 SPI Electrical Data/Timing
            1. 4.7.6.10.2.1 Serial Peripheral Interface (SPI) Timing
        11. 4.7.6.11 Inter-Integrated Circuit Serial Ports (I2C)
          1. 4.7.6.11.1 I2C Device-Specific Information
          2. 4.7.6.11.2 I2C Peripheral Registers Description(s)
          3. 4.7.6.11.3 I2C Electrical Data/Timing
            1. 4.7.6.11.3.1 Inter-Integrated Circuit (I2C) Timing
        12. 4.7.6.12 Universal Asynchronous Receiver/Transmitter (UART)
          1. 4.7.6.12.1 UART Peripheral Registers Description(s)
          2. 4.7.6.12.2 UART Electrical Data/Timing
        13. 4.7.6.13 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
          1. 4.7.6.13.1 USB0 [USB2.0] Electrical Data/Timing
        14. 4.7.6.14 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
        15. 4.7.6.15 Ethernet Media Access Controller (EMAC)
          1. 4.7.6.15.1 EMAC Peripheral Register Description(s)
            1. 4.7.6.15.1.1 EMAC Electrical Data/Timing
        16. 4.7.6.16 Management Data Input/Output (MDIO)
          1. 4.7.6.16.1 MDIO Register Description(s)
          2. 4.7.6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        17. 4.7.6.17 LCD Controller (LCDC)
          1. 4.7.6.17.1 LCD Interface Display Driver (LIDD Mode)
          2. 4.7.6.17.2 LCD Raster Mode
        18. 4.7.6.18 Host-Port Interface (UHPI)
          1. 4.7.6.18.1 HPI Device-Specific Information
          2. 4.7.6.18.2 HPI Peripheral Register Description(s)
          3. 4.7.6.18.3 HPI Electrical Data/Timing
        19. 4.7.6.19 Universal Parallel Port (uPP)
          1. 4.7.6.19.1 uPP Register Descriptions
          2. 4.7.6.19.2 uPP Electrical Data/Timing
        20. 4.7.6.20 Video Port Interface (VPIF)
          1. 4.7.6.20.1 VPIF Register Descriptions
          2. 4.7.6.20.2 VPIF Electrical Data/Timing
        21. 4.7.6.21 Enhanced Capture (eCAP) Peripheral
        22. 4.7.6.22 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
          1. 4.7.6.22.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
          2. 4.7.6.22.2 Trip-Zone Input Timing
        23. 4.7.6.23 Timers
          1. 4.7.6.23.1 Timer Electrical Data/Timing
        24. 4.7.6.24 Real Time Clock (RTC)
          1. 4.7.6.24.1 Clock Source
          2. 4.7.6.24.2 Real-Time Clock Register Descriptions
        25. 4.7.6.25 General-Purpose Input/Output (GPIO)
          1. 4.7.6.25.1 GPIO Register Description(s)
          2. 4.7.6.25.2 GPIO Peripheral Input/Output Electrical Data/Timing
          3. 4.7.6.25.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        26. 4.7.6.26 Programmable Real-Time Unit Subsystem (PRUSS)
          1. 4.7.6.26.1 PRUSS Register Descriptions
      7. 4.7.7 Emulation and Debug
        1. 4.7.7.1 JTAG Port Description
        2. 4.7.7.2 Scan Chain Configuration Parameters
        3. 4.7.7.3 Initial Scan Chain Configuration
        4. 4.7.7.4 IEEE 1149.1 JTAG
          1. 4.7.7.4.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
          2. 4.7.7.4.2 JTAG Test-Port Electrical Data/Timing
        5. 4.7.7.5 JTAG 1149.1 Boundary Scan Considerations
  5. 5Detailed Description
    1. 5.1 Device Overview
    2. 5.2 Device Compatibility
    3. 5.3 DSP Subsystem
      1. 5.3.1 C674x DSP CPU Description
      2. 5.3.2 DSP Memory Mapping
        1. 5.3.2.1 External Memories
        2. 5.3.2.2 DSP Internal Memories
        3. 5.3.2.3 C674x CPU
    4. 5.4 Memory Map Summary
    5. 5.5 Boot Modes
    6. 5.6 SYSCFG Module
    7. 5.7 Pullup/Pulldown Resistors
    8. 5.8 Reset
      1. 5.8.1 Power-On Reset (POR)
      2. 5.8.2 Warm Reset
    9. 5.9 Interrupts
      1. 5.9.1 DSP Interrupts
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
      1. 6.3.1 Receiving Notification of Documentation Updates
    4. 6.4 Community Resources
    5. 6.5 Trademarks
    6. 6.6 Electrostatic Discharge Caution
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Device and Documentation Support

6.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

    TMX Experimental device that is not necessarily representative of the final device's electrical specifications.
    TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification.
    TMS Fully-qualified production device.

Support tool development evolutionary flow:

    TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
    TMDS Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default).

Figure 6-1 provides a legend for reading the complete device.

SM320C6748-HIREL nomen_freon_c6748_sprs947.gif
A. BGA = Ball Grid Array
Figure 6-1 Device Nomenclature

6.2 Tools and Software

TI offers an extensive line of development tools for the device platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of the device applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator

For a complete listing of development-support tools for the device, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

6.3 Documentation Support

The following documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box.

    DSP Reference Guides
    SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.
    SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set.
    SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
    SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the device.
    SPRUGJ7SM320C6748-HIREL DSP System Reference Guide. Describes the System-on-Chip (SoC) system. The SoC system includes TI’s standard TMS320C674x Megamodule and several blocks of internal memory (L1P, L1D, and L2).
    SPRUGQ9TMS320C674x/OMAP-L1x Processor Security User's Guide. Provides an overview of the security concepts implemented on TI Basic Secure Boot devices.

6.3.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

6.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

6.5 Trademarks

BIOS, E2E are trademarks of Texas Instruments.

Windows is a registered trademark of Microsoft.

I2C Bus is a trademark of Phillips.

All other trademarks are the property of their respective owners.

6.6 Electrostatic Discharge Caution

esds-image

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

6.7 Glossary

    TI Glossary This glossary lists and explains terms, acronyms, and definitions.