SM320C6748-HIREL

ACTIVE

Product details

DSP type 1 C674x DSP (max) (MHz) 375 CPU 32-/64-bit Operating system SYS/BIOS Ethernet MAC 10/100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 105
DSP type 1 C674x DSP (max) (MHz) 375 CPU 32-/64-bit Operating system SYS/BIOS Ethernet MAC 10/100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 105
NFBGA (GWT) 361 256 mm² 16 x 16
  • 375-MHz C674x Fixed- and Floating-Point VLIW
    DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3
    (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned
      Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single
        Precision/32-Bit) and DP (IEEE Double
        Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock,
        Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or
        DP) Reciprocal Approximation (RCPxP) and
        Square-Root Reciprocal Approximation
        (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply
        Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-
        Bit Multiplies, Four 16 × 16-Bit Multiplies, or
        Eight 8 × 8-Bit Multiplies per Clock Cycle,
        and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and
      Program Redirection
  • Software Support
    • TI DSPBIOS™
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
    DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one
      of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address
        Space
      • 16-Bit mDDR SDRAM with 256-MB Address
        Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with
    Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD)
    Card Interfaces with Secure Data I/O (SDIO)
    Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide
    Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem
    (PRUSS)
    • Two Independent Programmable Real-Time Unit
      (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled via Software to
        Save Power
      • Register 30 of Each PRU is Exported From
        the Subsystem in Addition to the Normal R31
        Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock
        Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt, or
      ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single
      Raw (8-, 10-, and 12-Bit) Video Capture
      Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video
      Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and
      Data Converters
    • Data Width on Both Channels is 8- to 16-Bit
      Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START,
      ENABLE, and WAIT Controls
  • Serial ATA (SATA) Controller:
    • Supports SATA I (1.5 Gbps) and SATA II
      (3 Gbps)
    • Supports All SATA Power-Management
      Features
    • Hardware-Assisted Native Command Queueing
      (NCQ) for up to 32 Entries
    • Supports Port Multiplier and Command-Based
      Switching
  • Real-Time Clock (RTC) with 32-kHz Oscillator and
    Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each
    Configurable as Two 32-Bit
    Timers)
  • One 64-Bit General-Purpose or Watchdog Timer
    (Configurable as Two 32-Bit General-Purpose
    Timers)
  • Two Enhanced High-Resolution Pulse Width
    Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with
      Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
      Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary
      Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-
      Stamps
  • Packages:
    • 361-Ball SnPb PBGA [GWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature
  • 375-MHz C674x Fixed- and Floating-Point VLIW
    DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3
    (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned
      Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single
        Precision/32-Bit) and DP (IEEE Double
        Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock,
        Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or
        DP) Reciprocal Approximation (RCPxP) and
        Square-Root Reciprocal Approximation
        (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply
        Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-
        Bit Multiplies, Four 16 × 16-Bit Multiplies, or
        Eight 8 × 8-Bit Multiplies per Clock Cycle,
        and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and
      Program Redirection
  • Software Support
    • TI DSPBIOS™
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
    DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one
      of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address
        Space
      • 16-Bit mDDR SDRAM with 256-MB Address
        Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with
    Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD)
    Card Interfaces with Secure Data I/O (SDIO)
    Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide
    Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem
    (PRUSS)
    • Two Independent Programmable Real-Time Unit
      (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled via Software to
        Save Power
      • Register 30 of Each PRU is Exported From
        the Subsystem in Addition to the Normal R31
        Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock
        Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt, or
      ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single
      Raw (8-, 10-, and 12-Bit) Video Capture
      Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video
      Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and
      Data Converters
    • Data Width on Both Channels is 8- to 16-Bit
      Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START,
      ENABLE, and WAIT Controls
  • Serial ATA (SATA) Controller:
    • Supports SATA I (1.5 Gbps) and SATA II
      (3 Gbps)
    • Supports All SATA Power-Management
      Features
    • Hardware-Assisted Native Command Queueing
      (NCQ) for up to 32 Entries
    • Supports Port Multiplier and Command-Based
      Switching
  • Real-Time Clock (RTC) with 32-kHz Oscillator and
    Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each
    Configurable as Two 32-Bit
    Timers)
  • One 64-Bit General-Purpose or Watchdog Timer
    (Configurable as Two 32-Bit General-Purpose
    Timers)
  • Two Enhanced High-Resolution Pulse Width
    Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with
      Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
      Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary
      Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-
      Stamps
  • Packages:
    • 361-Ball SnPb PBGA [GWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature

The SM320C6748-HIREL fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects customers’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the TMS320C674x/OMAP-L1x Processor Security User&3146;s Guide (SPRUGQ9).

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The uPP provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The SM320C6748-HIREL fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects customers’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the TMS320C674x/OMAP-L1x Processor Security User&3146;s Guide (SPRUGQ9).

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The uPP provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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* Data sheet SM320C6748-HIREL Fixed- and Floating-Point Digital Signal Processor datasheet PDF | HTML 30 Jun 2016
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011

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Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Products
Automotive mmWave radar sensors
AWR1243 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 Automotive, second-generation 76-GHz to 81-GHz high-performance SoC for corner and long-range radar AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWRL1432 Single-chip low-power 76-GHz to 81-GHz automotive mmWave radar sensor AWRL6432 Single-chip low-power 57-GHz to 64-GHz automotive mmWave radar sensor
Industrial mmWave radar sensors
IWR1443 Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR1843AOP Single-chip 76-GHz to 81-GHz industrial radar sensor integrating antenna on package, DSP and MCU IWR2243 76-GHz to 81-GHz industrial high-performance MMIC IWR6243 57-GHz to 64-GHz industrial high-performance MMIC IWR6443 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP) IWRL1432 Single-chip low-power 76-GHz to 81-GHz industrial mmWave radar sensor IWRL6432 Single-chip low-power 57-GHz to 64-GHz industrial mmWave radar sensor
Arm Cortex-M0+ MCUs
MSPM0C1104 24 MHz Arm® Cortex®-M0+ MCU with 16-KB flash, 1-KB SRAM, 12-bit ADC MSPM0G1106 80MHz Arm M0+ MCU, 64KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, op-amp MSPM0G1107 80MHz Arm M0+ MCU, 128KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, op-amp MSPM0G1505 80MHz Arm M0+ MCU, 32KB Flash, 16KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, MATHACL MSPM0G1506 80MHz Arm M0+ MCU, 64KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, MATHACL MSPM0G1507 80MHz Arm M0+ MCU, 128KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, MATHACL MSPM0G3105 80MHz Arm M0+ MCU, 32KB Flash, 16KB SRAM, 2×12bit 4Msps ADC, op-amp, CAN-FD MSPM0G3106 80 MHz Arm® Cortex®-M0+ MCU with 64-KB Flash, 32-KB SRAM, ADC and CAN-FD MSPM0G3107 80MHz Arm M0+ MCU, 128KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, op-amp, CAN-FD MSPM0G3107-Q1 Automotive, 80-Mhz Arm® Cortex®-M0+ MCU with 128-KB flash, 32-KB SRAM, 12-bit ADC, CAN-FD and LIN MSPM0G3505 80MHz Arm M0+ MCU, 32KB Flash, 16KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, CAN-FD, MATHACL MSPM0G3506 80MHz Arm M0+ MCU, 64KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, CAN-FD, MATHACL MSPM0G3507 80MHz Arm M0+ MCU, 128KB Flash, 32KB SRAM, 2×12bit 4Msps ADC, DAC, 3×COMP, 3×op-amp, CAN-FD, MATHACL MSPM0G3507-Q1 Automotive, 80-Mhz Arm® Cortex®-M0+ MCU with 128-KB flash, 32-KB SRAM, 12-bit ADC,DAC,OPA and CAN-FD MSPM0L1105 32-MHz Arm® Cortex®-M0+ MCU with 32-KB flash, 4-KB SRAM, 12-bit ADC MSPM0L1106 32-MHz Arm® Cortex®-M0+ MCU with 64-KB flash, 4-KB SRAM, 12-bit ADC MSPM0L1303 32-MHz Arm® Cortex®-M0+ MCU with 8-KB flash, 2-KB SRAM, 12-bit ADC, comparator, OPA MSPM0L1304 32-MHz Arm® Cortex®-M0+ MCU with 16-KB flash, 2-KB SRAM, 12-bit ADC, comparator, OPA MSPM0L1305 32-MHz Arm® Cortex®-M0+ MCU with 32-KB flash, 4-KB SRAM, 12-bit ADC, comparator, OPA MSPM0L1305-Q1 Automotive 32-Mhz Arm® Cortex®-M0+ with 32-KB flash, 4-KB RAM, 12-bit ADC, OPA, LIN MSPM0L1306 32-MHz Arm® Cortex®-M0+ MCU with 64-KB flash, 4-KB SRAM, 12-bit ADC, comparator, OPA MSPM0L1306-Q1 Automotive 32-Mhz Arm® Cortex®-M0+ with 64-KB flash, 4-KB RAM, 12-bit ADC, OPA,LIN MSPM0L1343 32-MHz Arm® Cortex®-M0+ MCU with 8-KB flash, 2-KB SRAM, 12-bit ADC, comparator, TIA MSPM0L1344 32-MHz Arm® Cortex®-M0+ MCU with 16-KB flash, 2-KB SRAM, 12-bit ADC, comparator, TIA MSPM0L1345 32-MHz Arm® Cortex®-M0+ MCU with 32-KB flash, 4-KB SRAM, 12-bit ADC, comparator, TIA MSPM0L1346 32-MHz Arm® Cortex®-M0+ MCU with 64-KB flash, 4-KB SRAM, 12-bit ADC, comparator, TIA
Arm Cortex-M4 MCUs
MSP432E401Y SimpleLink™ 32-bit Arm Cortex-M4F MCU with ethernet, CAN, 1MB Flash and 256kB RAM MSP432E411Y SimpleLink™ 32-bit Arm Cortex-M4F MCU with ethernet, CAN, TFT LCD, 1MB Flash and 256kB RAM< TM4C1230C3PM High performance 32-bit ARM® Cortex®-M4F based MCU TM4C1230D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 24-kb RAM, CAN, 64-pin LQFP TM4C1230E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, CAN, 64-pin LQFP TM4C1230H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, 64-pin LQFP TM4C1231C3PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 32-kb Flash, 12-kb RAM, CAN, RTC, 64-pin LQFP TM4C1231D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 24-kb RAM, CAN, RTC, 64-pin LQFP TM4C1231D5PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 24-kb RAM, CAN, RTC, 100-pin LQFP TM4C1231E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 24-kb RAM, CAN, RTC, 64-pin LQFP TM4C1231E6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, CAN, RTC, 100-pin LQFP TM4C1231H6PGE 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, 144-pin LQFP TM4C1231H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, 64-pin LQFP TM4C1231H6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, 100-pin LQFP TM4C1232C3PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 32-kb Flash, 32-kb RAM, CAN, USB-D, 64-pin LQFP TM4C1232D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 12-kb RAM, CAN, USB-D, 64-pin LQFP TM4C1232E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 24-kb RAM, CAN, USB-D, 64-pin LQFP TM4C1232H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, USB-D, 64-pin LQFP TM4C1233C3PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 32-kb Flash, 32-kb RAM, CAN, RTC, USB-D, 64-pin LQFP TM4C1233D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 12-kb RAM, CAN, RTC, USB-D, 64-pin LQFP TM4C1233D5PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 24-kb RAM, CAN, RTC, USB-D, 100-pin LQFP TM4C1233E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 24-kb RAM, CAN, RTC, USB-D, 64-pin LQFP TM4C1233E6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, CAN, RTC, USB-D, 100-pin LQFP TM4C1233H6PGE 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB-D, 144-pin LQFP TM4C1233H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB-D, 64-pin LQFP TM4C1233H6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB-D, 100-pin LQFP TM4C1236D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 32-kb RAM, CAN, USB, 64-pin LQFP TM4C1236E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 24-kb RAM, CAN, USB, 64-pin LQFP TM4C1236H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, USB, 64-pin LQFP TM4C1237D5PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 32-kb RAM, CAN, RTC, USB, 64-pin LQFP TM4C1237D5PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 64-kb Flash, 24-kb RAM, CAN, RTC, USB, 100-pin LQFP TM4C1237E6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 24-kb RAM, CAN, RTC, USB, 64-pin LQFP TM4C1237E6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, CAN, RTC, USB, 100-pin LQFP TM4C1237H6PGE 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB, 144-pin LQFP TM4C1237H6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB, 64-pin LQFP TM4C1237H6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, CAN, RTC, USB, 100-pin LQFP TM4C123AE6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, 64-pin LQFP TM4C123AH6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, 64-pin LQFP TM4C123BE6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, RTC, 64-pin LQFP TM4C123BE6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, RTC, 100-pin LQFP TM4C123BH6NMR 32-bit Arm® Cortex®-M4F-based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, USB< TM4C123BH6PGE 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, 144-pin LQFP TM4C123BH6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, 64-pin LQFP TM4C123BH6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, 100-pin LQFP TM4C123BH6ZRB 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, 157-pin BGA TM4C123FE6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, USB, 64-pin LQFP TM4C123FH6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, USB, 64-pin LQFP TM4C123GE6PM 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 64-pin LQFP TM4C123GE6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 128-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 100-pin LQFP TM4C123GH6NMR 32-bit Arm® Cortex®-M4F-based MCU with 80-MHz, 256-kb flash, 32-kb RAM, 2x CAN, RTC, USB TM4C123GH6PGE 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 144-pin LQFP TM4C123GH6PM 32-bit Arm Cortex-M4F based MCU with 80 -MHz, 256 -KB Flash, 32 -KB RAM, 2 CAN, RTC, USB, 64-Pin TM4C123GH6PZ 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 100-pin LQFP TM4C123GH6ZRB 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 157-pin BGA TM4C123GH6ZXR 32-bit Arm Cortex-M4F based MCU with 80-MHz, 256-kb Flash, 32-kb RAM, 2x CAN, RTC, USB, 168-pin BGA TM4C1290NCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB TM4C1290NCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB TM4C1292NCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+MII TM4C1292NCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+MII TM4C1294KCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 512-kb Flash, 256-kb RAM, USB, ENET MAC+PHY TM4C1294NCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHZ, 1-MB flash, 256-KB RAM, USB, ENET MAC+PHY TM4C1294NCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+PHY TM4C1297NCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, LCD TM4C1299KCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 512-kb Flash, 256-kb RAM, USB, ENET MAC+PHY, LCD TM4C1299NCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+PHY, LCD TM4C129CNCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, AES TM4C129CNCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, AES TM4C129DNCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+MII, AES TM4C129DNCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+MII, AES TM4C129EKCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 512-kb Flash, 256-kb RAM, USB, ENET MAC+PHY, AES TM4C129ENCPDT 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+PHY, AES TM4C129ENCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+PHY, AES TM4C129LNCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-kb RAM, USB, ENET MAC+PHY, LCD, AES TM4C129XKCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 512-kb Flash, 256-kb RAM, USB, ENET MAC+PHY, LCD, AES TM4C129XNCZAD 32-bit Arm Cortex-M4F based MCU with 120-MHz, 1-MB Flash, 256-KB RAM, USB, ENET MAC+PHY, LCD, AES TMS470MF03107 16/32-bit RISC Flash microcontroller TMS470MF04207 16/32-bit RISC Flash microcontroller TMS470MF06607 16/32-bit RISC Flash microcontroller
Arm Cortex-R MCUs
AM2431 Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz AM2432 Dual-core Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz AM2434 Quad-core Arm® Cortex®-R5F-based MCU with industrial communications and security up to 800 MHz AM2631 Single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM2631-Q1 Automotive single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM2632 Dual-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM2632-Q1 Automotive dual-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM2634 Quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM2634-Q1 Automotive quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security AM263P4 Quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and expandable memory AM263P4-Q1 Automotive quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and expand AM2732 Dual-core Arm® Cortex-R5F based MCU with C66x DSP, ethernet and security up to 400 MHz AM2732-Q1 Automotive dual-core Arm® Cortex-R5F MCU up to 400 MHz with C66x DSP, Ethernet, safety, security RM41L232 16/32 Bit RISC Flash MCU, Arm Cortex-R4F RM42L432 16/32 Bit RISC Flash MCU, Arm Cortex-R4F RM44L520 16/32 Bit RISC Flash MCU, Arm Cortex-R4F RM44L920 16/32 Bit Arm Cortex-R4F Flash MCU, RISC RM46L430 16/32 Bit RISC Flash MCU, Cortex R4F, USB RM46L440 16/32 Bit RISC Flash MCU, Cortex R4F, EMAC RM46L450 16/32 Bit RISC Flash MCU, Cortex R4F, EMAC, USB RM46L830 16/32 Bit RISC Flash MCU, Cortex R4F, USB RM46L840 16/32 Bit RISC Flash MCU, Cortex R4F, EMAC RM46L850 16/32 Bit RISC Flash MCU, Cortex R4F, EMAC, USB RM46L852 16/32 Bit RISC Flash MCU, Cortex R4F, EMAC, USB RM48L530 16/32-Bit RISC Flash Microcontroller RM48L540 16/32-Bit RISC Flash Microcontroller RM48L730 16/32-Bit RISC Flash Microcontroller RM48L740 16/32-Bit RISC Flash Microcontroller RM48L940 16/32-Bit RISC Flash Microcontroller RM48L950 16/32-Bit RISC Flash Microcontroller RM48L952 16/32-Bit RISC Flash Microcontroller RM57L843 16/32 Bit Arm Cortex-R5F Flash MCU, RISC, EMAC SM320F2812-HT C2000™ High Temperature 32-bit MCU with 150 MHz, 256 KB Flash, EMIF TMS470R1A256 16/32-Bit RISC Flash Microcontroller TMS470R1A288 16/32-Bit RISC Flash Microcontroller TMS470R1A384 16/32-Bit RISC Flash Microcontroller TMS470R1A64 16/32-Bit RISC Flash Microcontroller TMS470R1B1M 16/32-Bit RISC Flash Microcontroller TMS470R1B512 16/32-Bit RISC Flash Microcontroller TMS470R1B768 16/32-Bit RISC Flash Microcontroller TMS5700404-Q1 TMS5700404-Q1 TMS5700405-Q1 TMS5700405-Q1 TMS5701203-Q1 TMS5701203-Q1 TMS570LC4357 16/32 Bit RISC Flash MCU, Arm Cortex-R5F, EMAC, FlexRay, Auto Q-100 TMS570LC4357-EP Enhanced product, 16/32 bit RISC flash MCU, Arm Cortex-R5F, EMAC, FlexRay TMS570LS0232 16/32 Bit RISC Flash MCU, Arm Cortex-R4, Auto Q-100 TMS570LS0332 16/32 Bit RISC Flash MCU, Arm Cortex-R4, Auto Q-100 TMS570LS0432 16/32 Bit RISC Flash MCU, Arm Cortex-R4, Auto Q-100 TMS570LS0714 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, Auto Q-100 TMS570LS0714-S High Performance 32-bit ARM Cortex-R5 based Microcontroller TMS570LS0914 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, Auto Q-100 TMS570LS10106 ARM Cortex-R4F Flash Microcontroller TMS570LS10116 ARM Cortex-R4F Flash Microcontroller TMS570LS10206 ARM Cortex-R4F Flash Microcontroller TMS570LS1114 16/32 Bit RISC Flash MCU, Cortex R4F, Auto Q100 TMS570LS1115 16/32 Bit RISC Flash MCU, Cortex R4F, Auto Q100, Flexray TMS570LS1224 16/32 Bit RISC Flash MCU, Cortex R4F, Auto Q100 TMS570LS1225 16/32 Bit RISC Flash MCU, Cortex R4F, Auto Q100, Flexray TMS570LS1227 16/32 Bit RISC Flash MCU, Cortex R4F, Auto Q100, Flexray, EMAC TMS570LS20206 ARM Cortex-R4F Flash Microcontroller TMS570LS20206-EP Enhanced Product 16- and 32-Bit RISC Flash Microcontroller TMS570LS20216 ARM Cortex-R4F Flash Microcontroller TMS570LS20216-EP Enhanced Product 16- and 32-Bit RISC Flash Microcontroller TMS570LS2124 16/32 Bit RISC Flash MCU, Arm Cortex-R4F TMS570LS2125 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, FlexRay TMS570LS2134 16/32 Bit RISC Flash MCU, Arm Cortex-R4F TMS570LS2135 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, FlexRay TMS570LS3134 16/32 Bit RISC Flash MCU, Arm Cortex-R4F TMS570LS3135 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, FlexRay TMS570LS3137 16/32 Bit RISC Flash MCU, Arm Cortex-R4F, EMAC, FlexRay TMS570LS3137-EP Enhanced Product 16/32 Bit RISC Flash Arm Cortex-R4F, EMAC, FlexRay
Sub-1 GHz wireless MCUs
CC1310 SimpleLink™ 32-bit Arm Cortex-M3 Sub-1 GHz wireless MCU with 128kB Flash CC1311P3 SimpleLink™ Arm® Cortex®-M4 Sub-1 GHz wireless MCU with 352-KB Flash and integrated +20dBm PA CC1311R3 SimpleLink™ Arm® Cortex®-M4 Sub-1 GHz wireless MCU with 352-kB flash CC1312R SimpleLink™ 32-bit Arm Cortex-M4F Sub-1 GHz wireless MCU with 352kB Flash CC1312R7 SimpleLink™ Arm® Cortex®-M4F multiprotocol Sub-1 GHz wireless MCU with 704-kB Flash CC1314R10 SimpleLink™ Arm® Cortex®-M33 Sub-1 GHz wireless MCU with 1-MB flash and up to 296 kB of SRAM CC1350 SimpleLink™ 32-bit Arm Cortex-M3 multiprotocol Sub-1 GHz & 2.4 GHz wireless MCU with 128kB Flash CC1352P SimpleLink™ Arm Cortex-M4F multiprotocol Sub-1 GHz & 2.4 GHz wireless MCU integrated power amplifier CC1352P7 SimpleLink™ Arm® Cortex®-M4F multiprotocol sub-1 GHz and 2.4-GHz wireless MCU integrated power amp CC1352R SimpleLink™ 32-bit Arm Cortex-M4F multiprotocol Sub-1 GHz & 2.4 GHz wireless MCU with 352kB Flash CC1354P10 SimpleLink™ Arm® Cortex®-M33 multiband wireless MCU with 1-MB flash, 296-KB SRAM & integrated PA CC1354R10 SimpleLink™ Arm® Cortex®-M33 multiband wireless MCU with 1-MB flash and up to 296-KB SRAM CC430F5123 16-bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 8kB Flash and 2kB RAM CC430F5125 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 16kB Flash and 2kB RAM CC430F5133 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 12-Bit ADC, 8kB Flash and 2kB RAM CC430F5135 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 12-Bit ADC, 16kB Flash and 2kB RAM CC430F5137 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 12-Bit ADC, 32kB Flash and 4kB RAM CC430F5143 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 10-bit ADC, 8kB Flash and 2kB RAM CC430F5145 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 10-bit ADC, 16kB Flash and 2kB RAM CC430F5147 16-Bit ultra-low-power CC430 Sub 1 GHz wireless MCU with 10-bit ADC, 32kB Flash and 4kB RAM
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