SLLS612F June   2004  – February 2023 SN65HVD485E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
    1.     6
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Driver
    6. 7.6  Electrical Characteristics: Receiver
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Supply Current
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 Dissipation Ratings
    12. 7.12 Typical Characteristics
      1.      Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Usage in an RS-485 Transceiver
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
        1. 10.1.1.1 Thermal Characteristics of IC Packages
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Switching Characteristics: Driver

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLHPropagation delay time, low-to-high-level outputRL = 54 Ω, CL = 50 pF (see Figure 8-4)30ns
tPHLPropagation delay time, high-to-low-level output30ns
trDifferential output signal rise time25ns
tfDifferential output signal fall time25ns
tsk(p)Pulse skew (|tPHL – tPLH|)5ns
tPZHPropagation delay time, high-impedance-to-high-level outputRL = 110 Ω, RE at 0 V (see Figure 8-5)150ns
tPHZPropagation delay time, high-level-to-high-impedance output100ns
tPZLPropagation delay time, high-impedance-to-low-level outputRL = 110 Ω, RE at 0 V (see Figure 8-6)150ns
tPLZPropagation delay time, low-level-to-high-impedance output100ns
tPZH(SHN)Propagation delay time, shutdown-to-high-level outputRL = 110 Ω, RE at VCC (see Figure 8-5)2600ns
tPZL(SHDN)Propagation delay time, shutdown-to-low-level outputRL = 110 Ω, RE at VCC (see Figure 8-6)2600ns