SLLSEA8 Data sheet

SLLSEA8A January 2012 – March 2016 SN65LVCP114

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

ZJA|167
- MPBGA19

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sllsea8a_oa

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage range⁽²⁾	–0.3	4	V
V_IN,DIFF	Differential voltage between xINx_P and xINx_N		±2.5	V
V_IN+, V_IN–	Voltage at xINx_P and xINx_N	–0.5	VCC + 0.5	V
V_IO	Voltage on control I/O pins	–0.3	VCC + 0.5	V
I_IN+ I_IN–	Continuous current at high-speed differential data inputs (differential)	–25	25	mA
I_OUT+ I_OUT–	Continuous current at high-speed differential data outputs	–25	25	mA
T_stg	Storage temperature	–55	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾⁽⁴⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

7.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
	Operating data rate, dR			14.2	Gbps
	Supply voltage, V_CC, 2.5-V nominal supply	2.375	2.5	2.625	V
	Supply voltage, V_CC, 3.3-V nominal supply	3.135	3.3	3.465	V
	PSNR BG, bandgap circuitry PSNR, 10 Hz–10 GHz	20			dB
CONTROL INPUTS
V_IH	High-level input voltage	0.8 × V_CC
V_IM	Mid-level input voltage	V_CC/2 – 0.3		V_CC/2 + 0.3	V
V_IL	Low- level input voltage			0.2 × V_CC	V
T_C	Junction temperature⁽¹⁾	–10		125	°C
	Maximum board temperature⁽¹⁾			See Table 1	°C

(1) Use of θJB and φJB are recommended for thermal calculations. For more information about traditional and new thermal metrics, see IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN65LVCC114	UNIT
		ZJA (NFBGA)
		167 PINS
R_θJA	Junction-to-ambient thermal resistance	38.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.55	°C/W
R_θJB	Junction-to-board thermal resistance	17.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	17.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics (V_CC 2.5 V ±5%)

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
POWER CONSUMPTION
PD_L	Device power dissipation, loopback mode	Ports A, B, and C in loopback mode with all 12 channels active. VOD = LOW	1800	2300	mW
PD_N	Device power dissipation, normal mode	Device configured in mux-demux mode with 8 channels active. VOD = LOW	1400	1800	mW
PD_OFF	Device power dissipation, lanes disabled	All 4 lanes disabled. See the I²C section for device configuration.	50		mW
PD_STB	Device power dissipation, standby	All 12 channels active, VOD = LOW, FAST_SW = HIGH. See the I²C section for device configuration.	1800	2300	mW

7.6 Electrical Characteristics (V_CC 3.3 V ±5%)

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
POWER CONSUMPTION
PD_L	Device power dissipation, loopback mode	Ports A, B, and C in loopback mode with all 12 channels active. VOD = LOW	2500	3150	mW
PD_N	Device power dissipation, normal mode	Device configured in mux-demux mode with 8 channels active. VOD = LOW	1800	2500	mW
PD_OFF	Device power dissipation, lanes disabled	All 4 lanes disabled. See the I²C section for device configuration.	50		mW
PD_STB	Device power dissipation, standby	All 12 channels active, VOD = LOW, FAST_SW = HIGH. See I²C section for device configuration.	2500	3150	mW

7.7 Electrical Characteristics (V_CC 3.3 V ±5%, 2.5 V ±5%)

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
CMOS DC SPECIFICATIONS
I_IH	High-level input current	V_IN = 0.9 × V_CC			80	µA
I_IL	Low-level input current	V_IN = 0.1 × V_CC	-80			µA
CML INPUTS (AINP[3:0], AINN[3:0], BINP[3:0], BINN[3:0], CINP[3:0], CINN[3:0])
r_IN	Differential input resistance	INx_P to INx_N		100		Ω
V_INPP	Input linear dynamic range	Gain = 0.5		1200		mVpp
V_ICM	Common-mode input voltage	Internally biased		V_CC – 0.3		V
SCD11	Input differential to common-mode conversion	100 MHz to 7.1GHz		–25		dB
SDD11	Differential input return loss	100 MHz to 7.1GHz		–10		dB
CML OUTPUTS (AOUTP[3:0], AOUTN[3:0], BOUTP[3:0], BOUTN[3:0], COUTP[3:0], COUTN[3:0])
V_OD	Output linear dynamic range	R_L = 100 Ω, V_OD = High		1200		mV_PP
V_OD	Output linear dynamic range	R_L = 100 Ω, V_OD = Low		600		mV_PP
V_OS	Output offset voltage	R_L = 100 Ω, 0 V applied at inputs			20	mV_PP
V_CM,RIP	Common-mode output ripple	K28.5 pattern at 14.2 Gbps, no interconnect loss, V_OD = HIGH		10	20	mV_RMS
V_OD,RIP	Differential path output ripple	K28.5 pattern at 14.2Gbps, no interconnect loss, V_IN = 1200 mVpp. Outputs squelched.			20	mV_PP
V_OCM	Output common mode voltage	See Figure 9		V_CC – 0.35		V
V_OC(SS)	Change in steady-state common-mode output voltage between logic states			±10		mV
t_PLH	Low-to-high propagation delay	See Figure 1		200		ps
t_PHL	High-to-low propagation delay	See Figure 1		200		ps
t_SK(O)	Inter-pair output skew ⁽²⁾	All outputs terminated with 100 Ω. See Figure 3		50		ps
t_SK(PP)	Part-to-part skew⁽³⁾				100	ps
t_R	Rise time	Input signal with 30-ps rise time, 20% to 80%. See Figure 2		31		ps
t_F	Fall time	Input signal with 30-ps fall time, 20% to 80%. See Figure 2		31		ps
SDD22	Differential output return loss	100 MHz to 7.1 GHz		–10		dB
SCC22	Common-mode output return loss	100 MHz to 7.1 GHz		–5		dB
t_SM	Multiplexer switch time	Mux to valid output (idle outputs are squelched)		100		ns
t_SM1	Multiplexer switch time	Mux to valid output (idle outputs are turned off)		10		μs
Ch_iso	Channel-to-channel isolation⁽⁴⁾	Frequency at 5.1625 GHz		52.2		dB
Ch_iso	Channel-to-channel isolation⁽⁴⁾	Frequency at 7.1 GHz		43.5		dB
OUT_NOISE	Output referred noise	10 MHz to 7.1 GHz. No other noise source present. V_OD = LOW			1500	µV_RMS
OUT_NOISE	Output referred noise	10 MHz to 7.1 GHz. No other noise source present. V_OD = HIGH			3000	µV_RMS
Vpre	Output pre-cursor pre-emphasis	Input signal with 3.75-dB pre-cursor and measured on the output signal. See Figure 4. Vpre = 20 log(V3/V2)		5		dB
Vpst	Output post-cursor pre-emphasis	Input signal with 12-dB post-cursor and measure on the output signal. See Figure 4. Vpst = 20 log(V1/V2)		14		dB
r_OT	Single-ended output resistance	Single-ended on-chip terminations to VCC, outputs are AC-coupled		50		Ω
r_OM	Output termination mismatch at 1 MHz				5%
EQUALIZATION
EQ_Gain	At 7.1 GHz input signal	Equalization gain, EQ = MAX	10	15		dB
DJ1	TX residual deterministic jitter at 10.3125 Gbps	Tx launch amplitude = 0.6 Vpp, EQ = 1.3 dB, VOD and GAIN are high. Test channel = 0". See Figure 11.		0.08		UIp-p
DJ2	TX residual deterministic jitter at 14.2 Gbps	Tx launch amplitude = 0.6 Vpp, EQ = 1.3 dB, VOD and GAIN are high. Test channel = 0". See Figure 11.		0.06		UIp-p
DJ3	RX residual deterministic jitter at 10.3125 Gbps	Tx launch amplitude = 0.6 Vpp, test channel = 12” (9-dB loss at 5 GHz), EQ = 13.9 dB, VOD and GAIN are high. See Figure 10.		0.04		UIp-p
DJ4	RX residual deterministic Jitter at 14.2 Gbps	Tx launch amplitude = 0.6 Vpp, test channel = 8" (9-dB loss at 7 GHz), EQ = 13.9 dB, VOD = LOW and GAIN = HIGH. See Figure 10.		0.08		UIp-p

(1) All typical values are at 25°C and with 2.5-V and 3.3-V supply, unless otherwise noted.

(2) t_SK(O)is the magnitude of the time difference between the channels within a Port. For more information, see SN65LVCP114 Guidelines for Skew Compensation, SLLA323.

(3) t_SK(PP)is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4) All noise sources added.

Figure 1. Propagation Delay, Input to Output

Figure 2. Output Rise and Fall Times

Figure 3. Output Inter-Pair Skew

Figure 4. VPRE and VPOST [The Test Pattern is 1111111100000000 (Eight 1s, Eight 0s)]

7.8 Typical Characteristics

Typical operating condition is at V_CC = 2.5 V and T_A = 25°C, no interconnect line at the output, and with default device settings (unless otherwise noted).