Product details


Type Mux Buffer Number of channels (#) 8 Input compatibility AC-coupling Speed (Max) (Gbps) 14.2 Operating temperature range (C) -40 to 85 Protocols Fibre Channel, General purpose open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Package | Pins | Size

NFBGA (ZJA) 167 144 mm² 12 x 12 open-in-new Find other Ethernet retimers, redrivers & mux-buffers


  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training
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The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

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Technical documentation

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Type Title Date
* Data sheet SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning datasheet (Rev. A) Apr. 01, 2016
Application note Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications May 15, 2020
Technical article Get Connected: Jitter Mar. 19, 2014
Application note The Benefits of Using Linear Equalization in Backplane and Cable Applications Jan. 31, 2013
User guide SN65LVCP114 EVM Graphical User Interface Guide Jan. 18, 2012
User guide SN65LVCP114 EVM User's Guide Jan. 18, 2012
Application note SN65LVCP114 Guidelines for Skew Compensation Jan. 17, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
Evaluation Module for SN65LVCP114
  • SN65LVCP114EVM Motherboard Features
  • Quad 1:2 / 2:1 Mux, Linear Redriver with Signal Conditioning
  • Signaling Rate up to 14.2Gbps
  • Runs from a 2.5V or 3.3V core supply

Software development

SLLC426.ZIP (25261 KB)

Design tools & simulation

SLLM168.ZIP (1157 KB) - S-Parameter Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
NFBGA (ZJA) 167 View options

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