Home Interface Ethernet ICs Ethernet retimers, redrivers & mux-buffers
Home
Interface
Ethernet ICs
Ethernet retimers, redrivers & mux-buffers

SN65LVCP114

ACTIVE

14.2-Gbps quad mux, linear-redriver with signal conditioning

Order now
Data sheet

SN65LVCP114

ACTIVE
Data sheet Order now

Product details

Type Mux Buffer Number of channels 8 Input compatibility AC-coupling Speed (max) (Gbps) 14.2 Protocols Fibre Channel, General purpose Operating temperature range (°C) -40 to 85
Type Mux Buffer Number of channels 8 Input compatibility AC-coupling Speed (max) (Gbps) 14.2 Protocols Fibre Channel, General purpose Operating temperature range (°C) -40 to 85
NFBGA (ZJA) 167 144 mm² 12 x 12
  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
    Rate
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
    Equalizer
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
    Saving
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training
  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data
    Rate
  • Linear Receiver Equalization Which Increases
    Margin at System Level of Decision Feedback
    Equalizer
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port
    to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm
    Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB
    Transmission Lines
  • Small Package Size Provides Board Real Estate
    Saving
  • Adjustable Output Swing Provides Flexible EMI
    and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability
    to Transparency for Link Training

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.
open-in-new Find other Ethernet retimers, redrivers & mux-buffers
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 7
Type Title Date
* Data sheet SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning datasheet (Rev. A) PDF | HTML 01 Apr 2016
More literature Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) 31 Jan 2023
Technical article Get Connected: Jitter 19 Mar 2014
More literature The Benefits of Using Linear Equalization in Backplane and Cable Applications 31 Jan 2013
User guide SN65LVCP114 EVM Graphical User Interface Guide 18 Jan 2012
EVM User's guide SN65LVCP114 EVM User's Guide 18 Jan 2012
More literature SN65LVCP114 Guidelines for Skew Compensation 17 Jan 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

GUI for evaluation module (EVM)

SN65LVCP114 EVM GUI

SLLC426.ZIP (25261 KB)
Download
Simulation model

SN65LVCP114 Sparameter Model

SLLM168.ZIP (1157 KB) - S-Parameter Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View options
Package Pins Download
NFBGA (ZJA) 167 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos