The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux,
linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly
compensates for channel loss in backplane and active-cable applications. The architecture of
SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing
digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux,
linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE
and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution
while at the same time extending the effectiveness of DFE.
SN65LVCP114 is configurable through GPIO or an I2C
A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.
The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm
The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of
SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent
lane switching. The receive equalization can be independently programmed for each of the ports. The
SN65LVCP114 supports loopback on all three ports.