SLLSF42A March   2018  – May 2018 SN65LVDS93B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SN65LVDS93B-Q1 set_hold_lls846.gif
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0 V.
Figure 4. Set Up and Hold Time Definition
SN65LVDS93B-Q1 test_load_lls846.gifFigure 5. Test Load and Voltage Definitions for LVDS Outputs
SN65LVDS93B-Q1 gray_scale_lls846.gif
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 6. 16 Grayscale Test Pattern
SN65LVDS93B-Q1 worst_case_lls846.gif
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 7. Worst-Case Power Test Pattern
SN65LVDS93B-Q1 timing_lls846.gif
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 8. SN65LVDS93B-Q1 Timing Definitions
SN65LVDS93B-Q1 out_clock_lls846.gifFigure 9. Output Clock Jitter Test Set Up
SN65LVDS93B-Q1 enable_time_lls846.gifFigure 10. Enable Time Waveforms
SN65LVDS93B-Q1 disable_time_lls846.gifFigure 11. Disable Time Waveforms