SCAS999 March   2024 SN74AHCT594-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
    10. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Wettable Flanks
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

Table 7-1 lists the functional modes of the SN74AHCT594-Q1.

Table 7-1 Function Table
INPUTS(1) FUNCTION
SER SRCLK SRCLR RCLK RCLR
X X X X L Output register is cleared
X X L X X Internal shift register is cleared
H/L ↑ H X X SER Data is loaded into first shift bit as H/L, data shifts from bit to bit within the internal shift register
X X H ↑ H Data is transferred from internal shift register to output register
H/L ↑ H ↑ H When SRCLK and RCLK are synchronous, Data is transferred from internal shift register to output register, internal shift register first bit is loaded with SER data H/L and data shifts from bit to bit within internal shift register
X ↓, L, H H X X Internal shift register remains in previous state
X X H ↓, L, H H Output register remains in previous state
(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care