SCES901D February 2019 – January 2024 SN74AXC1T45-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended triggering of downstream devices. For more information regarding the power up glitch performance of the AXC family of level translators, see the Power Sequencing for AXC Family of Devices application report