SCLS041J Data sheet

SCLS041J December 1982 – October 2021 SN54HC595 , SN74HC595

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

N|16
- MPDI002C
DW|16
- MSOI003I
PW|16
- MPDS361A
|
DB|16
- MPDS507A
D|16
- MPDS178G
NS|16
- MPDS551A

Thermal pad, mechanical data (Package|Pins)

DW|16
- QFND313D

Orderable Information

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

			V_CC	T_A = 25°C		SN54HC595		SN74HC595		UNIT
			V_CC	MIN	MAX	MIN	MAX	MIN	MAX	UNIT
f_clock	Clock frequency		2 V		6		4.2		5	MHz
			4.5 V		31		21		25
			6 V		36		25		29
t_w	Pulse duration	SRCLK or RCLK high or low	2 V	80		120		100		ns
			4.5 V	16		24		20
			6 V	14		20		17
		SRCLR low	2 V	80		120		100
			4.5 V	16		24		20
			6 V	14		20		17
t_su	Set-up time	SER before SRCLK↑	2 V	100		150		125		ns
			4.5 V	20		30		25
			6 V	17		25		21
		SRCLK↑ before RCLK↑⁽¹⁾	2 V	75		113		94
			4.5 V	15		23		19
			6 V	13		19		16
		SRCLR low before RCLK↑	2 V	50		75		65
			4.5 V	10		15		13
			6 V	9		13		11
		SRCLR high (inactive) before SRCLK↑	2 V	50		75		60
			4.5 V	10		15		12
			6 V	9		13		11
t_h	Hold time, SER after SRCLK↑		2 V	0		0		0		ns
			4.5 V	0		0		0
			6 V	0		0		0

(1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.

Figure 6-1 Timing Diagram