SCLS774 October   2019 SN74HCS72-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Benefits of Schmitt-trigger Inputs
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Positive and Negative Clamping Diodes
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Output Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Timing Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCS72QDRQ1 SOIC (14) 8.70 mm x 3.90 mm
SN74HCS72QPWRQ1 TSSOP (14) 5.00 mm x 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.