SCES218Y APRIL   1999  – November 2018 SN74LVC1G14

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Logic Diagram (Positive Logic) (DBV, DCK, DRL, DRY, DPW, and YZP Package)
      2.      Logic Diagram (Positive Logic) (YZV Package)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: –40°C to 85°C
    7. 6.7 Switching Characteristics: –40°C to 125°C
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPW|5
  • DBV|5
  • DSF|6
  • DCK|5
  • YZV|4
  • DRL|5
  • DRY|6
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

This single Schmitt-trigger inverter is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G14 device contains one inverter and performs the Boolean function Y = A. The device functions as an independent inverter with Schmitt-trigger inputs, so the device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals to provide hysteresis (ΔVT) which makes the device tolerant to slow or noisy input signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Device Information

ORDER NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G14DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1G14DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G14DRL SOT-5X3 (5) 1.60 mm × 1.20 mm
SN74LVC1G14DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G14DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1G14YZP DSBGA (5) 1.39 mm × 0.89 mm
SN74LVC1G14YZV DSBGA (4) 0.89 mm × 0.89 mm
SN74LVC1G14DPW X2SON (5) 0.80 mm x 0.80 mm