SLASF30 January   2022 TAA5212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Serial Interfaces
        1. 8.3.2.1 Control Serial Interfaces
        2. 8.3.2.2 Audio Serial Interfaces
          1. 8.3.2.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.2.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.2.2.3 Left-Justified (LJ) Interface
        3. 8.3.2.3 Using Multiple Devices With Shared Buses
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Programmable Microphone Bias
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 ADC Signal-Chain
          1. 8.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 8.3.7.1.2 Programmable Channel Gain Calibration
          3. 8.3.7.1.3 Programmable Channel Phase Calibration
          4. 8.3.7.1.4 Programmable Digital High-Pass Filter
          5. 8.3.7.1.5 Programmable Digital Biquad Filters
          6. 8.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 8.3.7.1.7 Configurable Digital Decimation Filters
            1. 8.3.7.1.7.1 Linear Phase Filters
              1. 8.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 8.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 8.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 8.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 8.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 8.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 8.3.9 Programmable Channel Phase Calibration
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 VEGA Registers
      2. 8.5.2 TAA5212 Registers
      3. 8.5.3 TAA5212 Registers
    6. 8.6 Feature Description
    7. 8.7 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.2 TAA5212 Registers

Table 8-106 lists the memory-mapped registers for the TAA5212 registers. All register offset addresses not listed in Table 8-106 should be considered as reserved locations and the register contents should not be modified.

Table 8-106 TAA5212 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x3DSP_CFG00x00DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]
0xDCLK_CFG00x00CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]
0xECHANNEL_CFG10x00CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]
0x17SRC_CFG0SRC configuration register 10x00SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]
0x18SRC_CFG1SRC configuration register 20x00SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]
0x1ELPAD_CFG1LPAD0x20LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
0x20LPAD_CFG1LPAD configuration register 10x00LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
0x24AGC_DRC_CFGAGC_DRC configuration register 20x00AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]
0x2CMIXER_CFG0MISC configuration register 00x00MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]
0x2DMISC_CFG0MISC configuration register 00x00MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]
0x2FINT_MASK0Interrupt Mask Register-00xFFINT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]
0x33INT_MASK5Interrupt Mask Register-30x30INT_MASK5 Register (Address = 0x33) [Reset = 0x30]
0x34INT_LTCH0Latched Interrupt Readback Register-00x00INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]
0x35CHx_LTCHSummary of Diagnostics0x00CHx_LTCH Register (Address = 0x35) [Reset = 0x00]
0x38ADC_CHx_OVRLD0x00ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]
0x3BINT_LTCH2Latched Interrupt Readback Register-30x00INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]
0x3CINT_LIVE0Live Interrupt Readback Register-00x00INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]
0x3DCHx_LIVESummary of Diagnostics0x00CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]
0x43INT_LIVE2Latched Interrupt Readback Register-30x00INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]
0x4EDIAG_CFG80xBADIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]
0x4FDIAG_CFG90x4BDIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]
0x55DIAGDATA_CFG0x00DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]
0x58DIAG_MON_MSB_MBIAS0x00DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]
0x59DIAG_MON_LSB_MBIAS0x01DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]
0x6ADIAG_MON_MSB_TEMP0x00DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]
0x6BDIAG_MON_LSB_TEMP0x0ADIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]
0x6CDIAG_MON_MSB_MBIAS_LOAD0x00DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]
0x6DDIAG_MON_LSB_MBIAS_LOAD0x0BDIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]
0x6EDIAG_MON_MSB_AVDD0x00DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]
0x6FDIAG_MON_LSB_AVDD0x0CDIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]
0x70DIAG_MON_MSB_GPA0x00DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]
0x71DIAG_MON_LSB_GPA0x0DDIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

8.5.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 8-107.

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The device memory map is divided into pages. This register sets the page.

Table 8-107 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

8.5.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 8-108.

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Table 8-108 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1DIS_DVOL_OTF_CHGR/W0bDisable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on
1d = Digital volume control changes not supported while ADC is powered-on.
0EN_BQ_OTF_CHGR/W0bEnable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes
1d = Enable on the fly biquad changes

8.5.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 8-109.

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Table 8-109 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CNT_TGT_CFG_OVR_PASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit.
1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available.
PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
6CNT_TGT_CFG_OVR_SASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit.
1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available.
SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
5RESERVEDR0bReserved bit; Write only reset value
4-3RESERVEDR/W00bReserved bits; Write only reset values
2PASI_USE_INT_FSYNCR/W0bFor Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
1SASI_USE_INT_FSYNCR/W0bFor Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
0RESERVEDR/W0bReserved bit; Write only reset value

8.5.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 8-110.

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Table 8-110 CHANNEL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7FORCE_DYN_MODE_CUST_MAX_CHR/W0bADC Force dynamic mode custom max channel
0d = In Dynamicmode , Max channel is based on ADC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3DYN_MODE_CUST_MAX_CH[3:0]R/W0000bADC Dynamic mode custom max channel configuration
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR000bReserved bits; Write only reset values

8.5.2.5 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 8-111.

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This register is configuration register 1 for SRC.

Table 8-111 SRC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SRC_ENR/W0bSRC enable config
0b = SRC disable
1b = SRC enable
6DIS_AUTO_SRC_DETR/W0bSRC auto detect config
0b = SRC auto detect enabled
1b = SRC auto detect disabled
5-0RESERVEDR000000bReserved bits; Write only reset value

8.5.2.6 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 8-112.

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This register is configuration register 2 for SRC.

Table 8-112 SRC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7MAIN_FS_CUSTOM_CFGR/W0bMain Fs custom config
0b = Main Fs is auto inferred
1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6MAIN_FS_SELECT_CFGR/W0bMain Fs select config
0b = PASI Fs shall be used as Main Fs
1b = SASI Fs shall be used as Main Fs
5-3MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = m is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved
2-0MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = n is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved

8.5.2.7 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 8-113.

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Low Power Activity Detection. Voice activity detection or Ultrasonic Activity detection configuration register 1

Table 8-113 LPAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD/UAD interrupt based ADC power up and ADC power down
2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down
Dont use
5-4LPAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity
1d = Channel 2 is monitored for VAD/UAD activity
2d = Channel 3 is monitored for VAD/UAD activity
3d = Channel 4 is monitored for VAD/UAD activity
3LPAD_SDOUT_INT_CFGR/W0bSDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function
1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded
2RESERVEDR0bReserved bit; Write only reset value
1LPAD_PD_DET_ENR/W0bEnable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording
1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0RESERVEDR/W0bReserved bit; Write only reset value

8.5.2.8 AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_DRC_CFG is shown in Table 8-114.

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This register is configuration register 2 for AGC_DRC.

Table 8-114 AGC_DRC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AGC_CH1_ENR/W0bAGC Channel 1 enable config
0d = disable
1d = enable
6AGC_CH2_ENR/W0bAGC Channel 2 enable config
0d = disable
1d = enable
5AGC_CH3_ENR/W0bAGC Channel 3 enable config
0d = disable
1d = enable
4AGC_CH4_ENR/W0bAGC Channel 4 enable config
0d = disable
1d = enable
3DRC_CH1_ENR/W0bDRC Channel 1 enable config
0d = disable
1d = enable
2DRC_CH2_ENR/W0bDRC Channel 2 enable config
0d = disable
1d = enable
1DRC_CH3_ENR/W0bDRC Channel 3 enable config
0d = disable
1d = enable
0DRC_CH4_ENR/W0bDRC Channel 4 enable config
0d = disable
1d = enable

8.5.2.9 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 8-115.

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This register is the MISC configuration register 0.

Table 8-115 MIXER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6EN_SIDE_CHAIN_MIXERR/W0bEnable Side Chain Mixer
0b = Disabled
1b = Enabled
5EN_ADC_CHANNEL_MIXERR/W0bEnable ADC Channel Mixer
0b = Disabled
1b = Enabled
4RESERVEDR/W0bReserved bit; Write only reset value
3-0RESERVEDR0000bReserved bits; Write only reset values

8.5.2.10 MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]

MISC_CFG0 is shown in Table 8-116.

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This register is the MISC configuration register 0.

Table 8-116 MISC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4EN_DRCR/W0bDRC enable config
0b = DRC disable
1b = DRC enable
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1DSP_VBAT_AVDD_SELR/W0bSAR data source select for DSP Limiter, BOP, DRC
0b = SAR VBAT data to DSP
1b = SAR AVDD data to DSP
0RESERVEDR/W0bReserved bit; Write only reset value

8.5.2.11 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 8-117.

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Interrupt masks.

Table 8-117 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bClock error interrupt mask.
0b = Don't Mask
1b = Mask
6INT_MASK0R/W1bPLL Lock interrupt mask.
0b = Don't Mask
1b = Mask
5RESERVEDR/W1bReserved bit; Write only reset value
4RESERVEDR/W1bReserved bit; Write only reset value
3RESERVEDR/W1bReserved bit; Write only reset value
2RESERVEDR/W1bReserved bit; Write only reset value
1RESERVEDR/W1bReserved bit; Write only reset value
0RESERVEDR/W1bReserved bit; Write only reset value

8.5.2.12 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 8-118.

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Interrupt masks.

Table 8-118 INT_MASK5 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK5R/W0bGPA up threshold fault mask.
0b = Don't Mask
1b = Mask
6INT_MASK5R/W0bGPA low threshold fault mask.
0b = Don't Mask
1b = Mask
5INT_MASK5R/W1bVAD power up detect interrupt mask.
0b = Don't Mask
1b = Mask
4INT_MASK5R/W1bVAD power down detect interrupt mask.
0b = Don't Mask
1b = Mask
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

8.5.2.13 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 8-119.

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Latched interrupt readback.

Table 8-119 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt due to clock error (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH0R0bInterrupt due to PLL Lock (self clearing bit)
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.14 CHx_LTCH Register (Address = 0x35) [Reset = 0x00]

CHx_LTCH is shown in Table 8-120.

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Channel level Diagnostics Latched Status

Table 8-120 CHx_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LTCHR0bStatus of Input CH1_LTCH.
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LTCHR0bStatus of Input CH2_LTCH.
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.15 ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]

ADC_CHx_OVRLD is shown in Table 8-121.

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Table 8-121 ADC_CHx_OVRLD Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3MASK_ADC_CH1_OVRLD_FLAGR/W0bADC CH1 OVRLD fault mask.
0b = Don't Mask
1b = Mask
2MASK_ADC_CH2_OVRLD_FLAGR/W0bADC CH2 OVRLD fault mask.
0b = Don't Mask
1b = Mask
1-0RESERVEDR00bReserved bits; Write only reset value

8.5.2.16 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 8-122.

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Latched interrupt readback.

Table 8-122 INT_LTCH2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH2R0bInterrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH2R0bInterrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt
1b = Interrupt
5INT_LTCH2R0bInterrupt due to VAD power up detect (self clearing bit).
0b = No interrupt
1b = Interrupt
4INT_LTCH2R0bInterrupt due to VAD power down detect (self clearing bit).
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.17 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 8-123.

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Latched interrupt readback.

Table 8-123 INT_LIVE0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE0R0bInterrupt due to clock error .
0b = No interrupt
1b = Interrupt
6INT_LIVE0R0bInterrupt due to PLL Lock
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.18 CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]

CHx_LIVE is shown in Table 8-124.

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Channel level Diagnostics Live Status

Table 8-124 CHx_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LIVER0bStatus of Input CH1_LIVE.
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LIVER0bStatus of Input CH2_LIVE.
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.19 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 8-125.

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Live interrupt readback.

Table 8-125 INT_LIVE2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE2R0bInterrupt due to GPA up threshold fault .
0b = No interrupt
1b = Interrupt
6INT_LIVE2R0bInterrupt due to GPA low threshold fault
0b = No interrupt
1b = Interrupt
5INT_LIVE2R0bInterrupt due to VAD power up detect .
0b = No interrupt
1b = Interrupt
4INT_LIVE2R0bInterrupt due to VAD power down detect .
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.5.2.20 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 8-126.

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Table 8-126 DIAG_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_UP_THRS_FLT_THRES[7:0]R/W10111010bGeneral Purpose Analog High Threshold
Default = ~ 2.6V
nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

8.5.2.21 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 8-127.

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Table 8-127 DIAG_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_LOW_THRS_FLT_THRES[7:0]R/W01001011bGeneral Purpose Analog Low Threshold
Default = ~ 0.2V
nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

8.5.2.22 DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]

DIAGDATA_CFG is shown in Table 8-128.

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Table 8-128 DIAGDATA_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000bReserved bits; Write only reset values
3IADC_DATA_IN_DIAG_REGSR/W0bIADC channel data in diagnostics channel data registers
0b= Disabled
1b= Enabled
2HOLD_IADC_DATAR/W0bHold IADC data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done
1OVRD_VBAT_TEMP_DATAR/W0bOverride VBAT and TEMP data
0b= Override Disabled
1b= Override Enabled
0HOLD_SAR_DATAR/W0bHold SAR data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done

8.5.2.23 DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]

DIAG_MON_MSB_MBIAS is shown in Table 8-129.

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Table 8-129 DIAG_MON_MSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.5.2.24 DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]

DIAG_MON_LSB_MBIAS is shown in Table 8-130.

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Table 8-130 DIAG_MON_LSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0001bChannel ID

8.5.2.25 DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]

DIAG_MON_MSB_TEMP is shown in Table 8-131.

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Table 8-131 DIAG_MON_MSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_TEMP[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.5.2.26 DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]

DIAG_MON_LSB_TEMP is shown in Table 8-132.

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Table 8-132 DIAG_MON_LSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_TEMP[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1010bChannel ID

8.5.2.27 DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]

DIAG_MON_MSB_MBIAS_LOAD is shown in Table 8-133.

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Table 8-133 DIAG_MON_MSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS_LOAD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.5.2.28 DIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]

DIAG_MON_LSB_MBIAS_LOAD is shown in Table 8-134.

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Table 8-134 DIAG_MON_LSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS_LOAD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1011bChannel ID

8.5.2.29 DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]

DIAG_MON_MSB_AVDD is shown in Table 8-135.

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Table 8-135 DIAG_MON_MSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_AVDD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.5.2.30 DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]

DIAG_MON_LSB_AVDD is shown in Table 8-136.

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Table 8-136 DIAG_MON_LSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_AVDD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1100bChannel ID

8.5.2.31 DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]

DIAG_MON_MSB_GPA is shown in Table 8-137.

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Table 8-137 DIAG_MON_MSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_GPA[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.5.2.32 DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

DIAG_MON_LSB_GPA is shown in Table 8-138.

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Table 8-138 DIAG_MON_LSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_GPA[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1101bChannel ID