SLASET3A April   2019  – August 2019 TAS2563

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  I2C Timing Requirements
    7. 7.7  SPI Timing Requirements
    8. 7.8  PDM Port Timing Requirements
    9. 7.9  TDM Port Timing Requirements
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  PurePath Console 3 Software
      2. 9.3.2  Device Mode and Address Selection
      3. 9.3.3  General I2C Operation
      4. 9.3.4  General SPI Operation
        1. Table 1. Command Word
      5. 9.3.5  Single-Byte and Multiple-Byte Transfers
      6. 9.3.6  Single-Byte Write
      7. 9.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 9.3.8  Single-Byte Read
      9. 9.3.9  Multiple-Byte Read
      10. 9.3.10 Register Organization
      11. 9.3.11 Operational Modes
        1. 9.3.11.1 Hardware Shutdown
        2. 9.3.11.2 Software Shutdown
        3. 9.3.11.3 Mute
        4. 9.3.11.4 Active
        5. 9.3.11.5 Perform Load Diagnostics
        6. 9.3.11.6 Mode Control and Software Reset
      12. 9.3.12 Faults and Status
      13. 9.3.13 Power Sequencing Requirements
      14. 9.3.14 Digital Input Pull Downs
    4. 9.4 Device Functional Modes
      1. 9.4.1 PDM Input
      2. 9.4.2 TDM Port
      3. 9.4.3 Playback Signal Path
        1. 9.4.3.1 Digital Signal Processor
        2. 9.4.3.2 High Pass Filter
        3. 9.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 9.4.3.4 Auto-mute During Idle Channel Mode
        5. 9.4.3.5 Auto-start/stop on Audio Clocks
        6. 9.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 9.4.3.7 Class-D Settings
      4. 9.4.4 SAR ADC
      5. 9.4.5 IV Sense
      6. 9.4.6 Load Diagnostics
      7. 9.4.7 Clocks and PLL
      8. 9.4.8 Thermal Foldback
    5. 9.5 Register Maps
      1. 9.5.1  Register Summary Table Page=0x00
      2. 9.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
        1. Table 90. Device Page Field Descriptions
      3. 9.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
        1. Table 91. Software Reset Field Descriptions
      4. 9.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
        1. Table 92. Power Control Field Descriptions
      5. 9.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
        1. Table 93. Playback Configuration 1 Field Descriptions
      6. 9.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
        1. Table 94. Misc Configuration 1 Field Descriptions
      7. 9.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
        1. Table 95. Misc Configuration 2 Field Descriptions
      8. 9.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
        1. Table 96. TDM Configuration 0 Field Descriptions
      9. 9.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
        1. Table 97. TDM Configuration 1 Field Descriptions
      10. 9.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
        1. Table 98. TDM Configuration 2 Field Descriptions
      11. 9.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
        1. Table 99. TDM Configuration 3 Field Descriptions
      12. 9.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
        1. Table 100. TDM Configuration 4 Field Descriptions
      13. 9.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
        1. Table 101. TDM Configuration 5 Field Descriptions
      14. 9.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
        1. Table 102. TDM Configuration 6 Field Descriptions
      15. 9.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
        1. Table 103. TDM Configuration 7 Field Descriptions
      16. 9.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
        1. Table 104. TDM Configuration 8 Field Descriptions
      17. 9.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
        1. Table 105. TDM Configuration 9 Field Descriptions
      18. 9.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
        1. Table 106. TDM Configuration 10 Field Descriptions
      19. 9.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
        1. Table 107. TDM Clock detection monitor Field Descriptions
      20. 9.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
        1. Table 108. Limiter Configuration 0 Field Descriptions
      21. 9.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
        1. Table 109. Limiter Configuration 1 Field Descriptions
      22. 9.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
        1. Table 110. Brown Out Prevention 0 Field Descriptions
      23. 9.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
        1. Table 111. Brown Out Prevention 2 Field Descriptions
      24. 9.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
        1. Table 112. Boost Current limiter and ICLA Field Descriptions
      25. 9.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
        1. Table 113. Inter Chip Limiter Alignment 0 Field Descriptions
      26. 9.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
        1. Table 114. Inter Chip Limiter Alignment 0 Field Descriptions
      27. 9.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
        1. Table 115. Inter Chip Limiter Alignment 1 Field Descriptions
      28. 9.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
        1. Table 116. Interrupt Mask 0 Field Descriptions
      29. 9.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
        1. Table 117. Interrupt Mask 1 Field Descriptions
      30. 9.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
        1. Table 118. Interrupt Mask 2 Field Descriptions
      31. 9.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
        1. Table 119. Interrupt Mask 3 Field Descriptions
      32. 9.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
        1. Table 120. Live Interrupt Readback 0 Field Descriptions
      33. 9.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
        1. Table 121. Live Interrupt Readback 1 Field Descriptions
      34. 9.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
        1. Table 122. Live Interrupt Readback 2 Field Descriptions
      35. 9.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
        1. Table 123. Live Interrupt Readback 3 Field Descriptions
      36. 9.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
        1. Table 124. Latched Interrupt Readback 0 Field Descriptions
      37. 9.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
        1. Table 125. Latched Interrupt Readback 1 Field Descriptions
      38. 9.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
        1. Table 126. Latched Interrupt Readback 2 Field Descriptions
      39. 9.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
        1. Table 127. Latched Interrupt Readback 3 Field Descriptions
      40. 9.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
        1. Table 128. SAR ADC Conversion 0 Field Descriptions
      41. 9.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
        1. Table 129. SAR ADC Conversion 1 Field Descriptions
      42. 9.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
        1. Table 130. SAR ADC Conversion 2 Field Descriptions
      43. 9.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
        1. Table 131. Field Descriptions
      44. 9.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
        1. Table 132. Digital Input Pin Pull Down Field Descriptions
      45. 9.5.45 MISC (page=0x00 address=0x32) [reset=80h]
        1. Table 133. Misc Configuration Field Descriptions
      46. 9.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
        1. Table 134. Boost Configure 1 Field Descriptions
      47. 9.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
        1. Table 135. Boost Configure 2 Field Descriptions
      48. 9.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
        1. Table 136. Boost Configure 3 Field Descriptions
      49. 9.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
        1. Table 137. Field Descriptions
      50. 9.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
        1. Table 138. Tone Generator Field Descriptions
      51. 9.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
        1. Table 139. Boost ILIM configuration-0 Field Descriptions
      52. 9.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
        1. Table 140. Field Descriptions
      53. 9.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
        1. Table 141. Field Descriptions
      54. 9.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
        1. Table 142. Field Descriptions
      55. 9.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
        1. Table 143. Field Descriptions
      56. 9.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
        1. Table 144. Field Descriptions
      57. 9.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
        1. Table 145. Field Descriptions
      58. 9.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
        1. Table 146. SAR ADC Conversion 0 Field Descriptions
      59. 9.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
        1. Table 147. SAR ADC Conversion 1 Field Descriptions
      60. 9.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
        1. Table 148. Revision and PG ID Field Descriptions
      61. 9.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
        1. Table 149. I2C Checksum Field Descriptions
      62. 9.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
        1. Table 150. Device Book Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Mono/Stereo Configuration
        2. 10.2.2.2 Boost Converter Passive Devices
        3. 10.2.2.3 EMI Passive Devices
        4. 10.2.2.4 Miscellaneous Passive Devices
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power Supply Sequencing
      1. 11.2.1 Boost Supply Details
      2. 11.2.2 External Boost Mode (Boost Bypass Mode)
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • High performance Class-D amplifier
    • 6.1-W 1% THD+N (4 Ω at 3.6 V)
    • 5-W 1% THD+N (8 Ω at 3.6 V)
    • Boost bypass mode: 10 W(12 W) at 1% (10%) THD+ N (4 Ω,12 V)
  • 15-µVrms A-weighted idle channel noise
  • 112.5dB SNR at 1% THD+N (8 Ω)
  • 100dB PSRR with 200-mVPP ripple at 20Hz to 20 kHz
  • 83.5% Efficiency at 1 W (8 Ω, VBAT = 4.2 V)
  • < 1-µA HW Shutdown VBAT current
  • Speaker voltage and current sense
  • VBAT Tracking peak voltage limiter with brown-out prevention
  • Dedicated real-time DSP for speaker protection
    • Thermal and excursion protection
    • Detects leak and damaged speaker
  • 14.47-kHz to96-kHz Sample rates
  • 2 PDM MIC Inputs
  • Flexible user interfaces
    • I2S/TDM: 8 Channels (32 bit / 96 kHz)
    • I2C: Selectable addresses
  • MCLK Free operation
  • Two 2.54 to 6.76 MHz PDM inputs
  • Advanced brown-out prevention
  • Power supplies
    • VBAT: 2.7 V to 5.5 V
    • VDD: 1.65 V to 1.95 V
    • IOVDD: 1.65 V to 3.6 V
  • Spread-spectrum low EMI mode
  • Thermal and overcurrent protection
  • 42-Ball, 0.4 mm pitch, DSBGA package