SLASET3D April   2019  – January 2024 TAS2563

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2C Timing Requirements
    7. 5.7  SPI Timing Requirements
    8. 5.8  PDM Port Timing Requirements
    9. 5.9  TDM Port Timing Requirements
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PurePath Console 3 Software
      2. 7.3.2  Device Mode and Address Selection
      3. 7.3.3  General I2C Operation
      4. 7.3.4  General SPI Operation
      5. 7.3.5  Single-Byte and Multiple-Byte Transfers
      6. 7.3.6  Single-Byte Write
      7. 7.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 7.3.8  Single-Byte Read
      9. 7.3.9  Multiple-Byte Read
      10. 7.3.10 Register Organization
      11. 7.3.11 Operational Modes
        1. 7.3.11.1 Hardware Shutdown
        2. 7.3.11.2 Software Shutdown
        3. 7.3.11.3 Mute
        4. 7.3.11.4 Active
        5. 7.3.11.5 Perform Load Diagnostics
        6. 7.3.11.6 Mode Control and Software Reset
      12. 7.3.12 Faults and Status
      13. 7.3.13 Digital Input Pull Downs
    4. 7.4 Device Functional Modes
      1. 7.4.1 PDM Input
      2. 7.4.2 TDM Port
      3. 7.4.3 Playback Signal Path
        1. 7.4.3.1 Digital Signal Processor
        2. 7.4.3.2 High Pass Filter
        3. 7.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 7.4.3.4 Auto-mute During Idle Channel Mode
        5. 7.4.3.5 Auto-start/stop on Audio Clocks
        6. 7.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 7.4.3.7 Class-D Settings
      4. 7.4.4 SAR ADC
      5. 7.4.5 Boost
      6. 7.4.6 IV Sense
      7. 7.4.7 Load Diagnostics
      8. 7.4.8 Clocks and PLL
      9. 7.4.9 Thermal Foldback
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table Page=0x00
      2. 7.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 7.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 7.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 7.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 7.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 7.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 7.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 7.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
      1. 9.2.1 Boost Supply Details
      2. 9.2.2 External Boost Mode (Boost Bypass Mode)
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|42
  • RPP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.11 Typical Characteristics

At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30 µH, unless otherwise noted.

Note: All the characteristics specified for PVDD = 16 V reffer to the DSBGA package.
GUID-918FAA60-448E-4743-B08E-9FB9E151AD7E-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-5 THD+N vs Output Power (DSBGA Package)
GUID-9CD7C904-7CE8-4A87-B4FB-EDB95663244F-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-7 THD+N vs Output Power (DSBGA Package)
GUID-ECD2986E-73D4-4501-AA37-A1E4E40378F1-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-9 THD+N vs Output Power
GUID-DE027260-CCDA-427B-ADAD-C6CEBF8CDA96-low.gif
RL = 4 Ω + 30 µH FIN = 6.667 kHz
Figure 5-11 THD+N vs Output Power (DSBGA Package)
GUID-D29A97C2-791E-4250-A901-4E7CE6F15684-low.gif
RL = 8 Ω + 30 µH FIN = 6.667 kHz
Figure 5-13 THD+N vs Output Power (DSBGA Package)
GUID-4FCE0DFD-F7AA-432E-BAC2-C753CCE1BB36-low.gif
RL = 4 Ω + 30 µH FIN = 6.667 kHz
Figure 5-15 THD+N vs Output Power
GUID-AEA2A003-4CFF-44C6-A3AE-A02444A110F7-low.gif
RL = 4 Ω + 30 µH P = 0.1 W
Figure 5-17 THD+N vs Frequency
GUID-1A6CBD52-FD22-439C-8B49-62801DFF9E23-low.gif
RL = 4 Ω + 30 µH P = 1 W
Figure 5-19 THD+N vs Frequency
GUID-6C35880F-8643-4E64-A647-50B1A7A5AB3D-low.gif
Figure 5-21 Idle Channel Noise (A-Weighted) vs VBAT
GUID-ACA75742-D3F9-497D-AF78-63DD17752D87-low.gif
RL = 8 Ω + 30 µH FS = 48 kHz
Figure 5-23 Amplitude vs Frequency
GUID-110A1958-44F1-4ECF-AC4C-24705DDE1D2E-low.gif
RL = 4 Ω + 30 µH
Figure 5-25 Max Output Power vs THD+N
GUID-C565AC11-FA7D-4EFB-A00B-0D2AFDC2B71A-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-27 Efficiency vs Output Power
GUID-090FE9DF-3FCF-4574-BED5-2B44485AE3A0-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz Bypass Mode
Figure 5-29 Efficiency vs Output Power
GUID-0CFEAC63-6402-46A7-8203-1EB7529EFAE8-low.gif
RL = 8 Ω + 30 µH Idle Channel
Figure 5-31 AVDD PSRR vs Frequency
GUID-416BD7F7-92DC-401B-9DB0-C9FC127D2AC9-low.gif
RL = 8 Ω + 30 µH Idle Channel
Figure 5-33 PVDD PSRR vs Frequency
GUID-20210226-CA0I-LSQR-BGDL-HGZQF6RXDGWP-low.png
Idle Channel
Figure 5-35 AVDD Idle Current vs AVDD (QFN Package)
GUID-6F38450A-207B-46DD-87A0-E55AA400AA25-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-37 I-sense THD+N vs Output Power (DSBGA Package)
GUID-F75DBC4B-B05F-4A60-AC1E-BA6E93074095-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-39 I-sense THD+N vs Output Power (DSBGA Package)
GUID-62DD52F0-F27E-4E85-A6ED-F23111DC2686-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-41 I-sense Linearity vs Output Power
GUID-51DA435B-2B83-4946-8687-C66AB3E8DDE1-low.gif
RL = 4 Ω + 30 µH P = 1 W
Figure 5-43 I-sense THD+N vs Frequency (DSBGA Package)
GUID-D912F9DD-E8BF-4452-BD77-58E405BDC6E0-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-45 I-sense THD+N vs Frequency (DSBGA Package)
GUID-9D18F18D-78A2-4092-B13D-A85570420C28-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-47 V-sense THD+N vs Output Power
GUID-1DCE4612-B66D-4D52-8300-74BFDEEFFB22-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-49 V-sense Linearity vs Output Power
GUID-2BCA1D1E-BCAE-4EFA-8ED2-B25FAB388921-low.gif
RL = 4 Ω + 30 µH P = 1 W
Figure 5-51 V-sense THD+N vs Frequency
GUID-1591141B-4131-473C-A0FF-F755BF59C439-low.gif
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-53 V/I-sense Linearity vs Output Power
GUID-BF976147-46D8-4CB5-941F-021F16CD9189-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-55 I-sense Linearity vs Temperature
GUID-095CCEFB-A490-498C-9AA8-56C0537F6C4E-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-57 V/I-sense Linearity vs Temperature
GUID-20210226-CA0I-NKQ0-1XVV-GZB82P5MSWKQ-low.png
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-6 THD+N vs Output Power (QFN Package)
GUID-20210212-CA0I-XCXP-BKP6-QG561HNVBXS0-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-8 THD+N vs Output Power (QFN Package)
GUID-54EF1D6D-E9A3-4B04-B87B-A8E916F7604E-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-10 THD+N vs Output Power
GUID-20210212-CA0I-KC8D-JWVH-DNJJNLVGJ0CS-low.gif
RL = 4 Ω + 30 µH FIN = 6.667 kHz
Figure 5-12 THD+N vs Output Power (QFN Package)
GUID-20210212-CA0I-GQRM-NXWT-CQSL77LHNHVR-low.gif
RL = 8 Ω + 30 µH FIN = 6.667 kHz
Figure 5-14 THD+N vs Output Power (QFN Package)
GUID-CBE765F0-78D0-4080-A5DE-10FE51D6ADCE-low.gif
RL = 8 Ω + 30 µH FIN = 6.667 kHz
Figure 5-16 THD+N vs Output Power
GUID-39857B67-4762-48BB-9703-87BF67DAB37E-low.gif
RL = 8 Ω + 30 µH P = 0.1 W
Figure 5-18 THD+N vs Frequency
GUID-48AB2B71-0BAB-4A3A-91A9-F28C475205E3-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-20 THD+N vs Frequency
GUID-20210226-CA0I-FR5C-HJLX-D0MPPMSS1ZWC-low.png
Boost Bypass
Figure 5-22 Idle Channel Noise (A-Weighted) vs PVDD
GUID-20210212-CA0I-LQRV-5VSV-RN0GGJF8LRPH-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz P = 1 W
Figure 5-24 FFT Signal Plot
GUID-2388CC4F-6375-494F-BE95-71DCC72F4CBA-low.gif
RL = 8 Ω + 30 µH
Figure 5-26 Max Output Power vs THD+N
GUID-2861A09C-4C7A-46AF-A5B8-71A095B675A9-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-28 Efficiency vs Output Power
GUID-043FFD1C-CB75-4212-889D-50E3CB5DC4E7-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz Bypass Mode
Figure 5-30 Efficiency vs Output Power
GUID-BCC3571E-6F5F-4D57-AC1D-BB1A4F3B6ECC-low.gif
RL = 8 Ω + 30 µH Idle Channel
Figure 5-32 VBAT PSRR vs Frequency
GUID-0D507590-BAC4-4277-A3AD-6D3D8757C15E-low.gif
Idle Channel
Figure 5-34 AVDD Idle Current vs AVDD (DSBGA Package)
GUID-20210226-CA0I-LN00-FRZD-KNCJRMWKDVTM-low.png
Idle Channel
Figure 5-36 VBAT Idle Current vs VBAT
GUID-20210226-CA0I-J072-9JVG-54FXTS0KJXR6-low.png
RL = 4 Ω + 30 µH FIN = 1 kHz
Figure 5-38 I-sense THD+N vs Output Power (QFN Package)
GUID-20210226-CA0I-VPSV-VLWQ-F6NCXMDH0MZG-low.png
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-40 I-sense THD+N vs Output Power (QFN Package)
GUID-CE77C022-96B6-4999-ADE0-086F207034CE-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-42 I-sense Linearity vs Output Power
GUID-20210226-CA0I-CTW5-M9NT-LXDKGLLCF1J9-low.png
RL = 4 Ω + 30 µH P = 1 W
Figure 5-44 I-sense THD+N vs Frequency (QFN Package)
GUID-20210226-CA0I-LHKS-XNQZ-9S1LCGVGK1XR-low.png
RL = 8 Ω + 30 µH P = 1 W
Figure 5-46 I-sense THD+N vs Frequency (QFN Package)
GUID-2735B063-8555-4091-90F8-BA0887E61951-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-48 V-sense THD+N vs Output Power
GUID-73E2BBC3-F530-45FE-87F3-972BC294172E-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-50 V-sense Linearity vs Output Power
GUID-0F6E1EA3-C5A6-4ED3-ABFC-C22236A8F25E-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-52 V-sense THD+N vs Frequency
GUID-6F0720E6-2018-433B-878B-9E729920383F-low.gif
RL = 8 Ω + 30 µH FIN = 1 kHz
Figure 5-54 V/I-sense Linearity vs Output Power
GUID-A20BD392-6BFC-4271-A0AE-B9A88C1713F9-low.gif
RL = 8 Ω + 30 µH P = 1 W
Figure 5-56 V-sense Linearity vs Temperature