SLASET3D April 2019 – January 2024 TAS2563
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Addr | Register | Description | Section |
0x00 | PAGE | Device Page | Section 7.5.2 |
0x01 | SW_RESET | Software Reset | Section 7.5.3 |
0x02 | PWR_CTL | Power Control | Section 7.5.4 |
0x03 | PB_CFG1 | Playback Configuration 1 | Section 7.5.5 |
0x04 | MISC_CFG1 | Misc Configuration 1 | Section 7.5.6 |
0x05 | MISC_CFG2 | Misc Configuration 2 | Section 7.5.7 |
0x06 | TDM_CFG0 | TDM Configuration 0 | Section 7.5.8 |
0x07 | TDM_CFG1 | TDM Configuration 1 | Section 7.5.9 |
0x08 | TDM_CFG2 | TDM Configuration 2 | Section 7.5.10 |
0x09 | TDM_CFG3 | TDM Configuration 3 | Section 7.5.11 |
0x0A | TDM_CFG4 | TDM Configuration 4 | Section 7.5.12 |
0x0B | TDM_CFG5 | TDM Configuration 5 | Section 7.5.13 |
0x0C | TDM_CFG6 | TDM Configuration 6 | Section 7.5.14 |
0x0D | TDM_CFG7 | TDM Configuration 7 | Section 7.5.15 |
0x0E | TDM_CFG8 | TDM Configuration 8 | Section 7.5.16 |
0x0F | TDM_CFG9 | TDM Configuration 9 | Section 7.5.17 |
0x10 | TDM_CFG10 | TDM Configuration 10 | Section 7.5.18 |
0x11 | DSP Mode & TDM_DET | TDM Clock detection monitor | Section 7.5.19 |
0x12 | LIM_CFG0 | Limiter Configuration 0 | Section 7.5.20 |
0x13 | LIM_CFG1 | Limiter Configuration 1 | Section 7.5.21 |
0x14 | DSP FREQUENCY & BOP_CFG0 | Brown Out Prevention 0 | Section 7.5.22 |
0x15 | BOP_CFG0 | Brown Out Prevention 2 | Section 7.5.23 |
0x16 | BIL_and_ICLA_CFG0 | Boost Current limiter and ICLA | Section 7.5.24 |
0x17 | BIL_ICLA_CFG1 | Inter Chip Limiter Alignment 0 | Section 7.5.25 |
0x18 | GAIN_ICLA_CFG0 | Inter Chip Limiter Alignment 0 | Section 7.5.26 |
0x19 | ICLA_CFG1 | Inter Chip Limiter Alignment 1 | Section 7.5.27 |
0x1A | INT_MASK0 | Interrupt Mask 0 | Section 7.5.28 |
0x1B | INT_MASK1 | Interrupt Mask 1 | Section 7.5.29 |
0x1C | INT_MASK2 | Interrupt Mask 2 | Section 7.5.30 |
0x1D | INT_MASK3 | Interrupt Mask 3 | Section 7.5.31 |
0x1F | INT_LIVE0 | Live Interrupt Readback 0 | Section 7.5.32 |
0x20 | INT_LIVE1 | Live Interrupt Readback 1 | Section 7.5.33 |
0x21 | INT_LIVE3 | Live Interrupt Readback 2 | Section 7.5.34 |
0x22 | INT_LIVE4 | Live Interrupt Readback 3 | Section 7.5.35 |
0x24 | INT_LTCH0 | Latched Interrupt Readback 0 | Section 7.5.36 |
0x25 | INT_LTCH1 | Latched Interrupt Readback 1 | Section 7.5.37 |
0x26 | INT_LTCH3 | Latched Interrupt Readback 2 | Section 7.5.38 |
0x27 | INT_LTCH4 | Latched Interrupt Readback 3 | Section 7.5.39 |
0x2A | VBAT_MSB | SAR ADC Conversion 0 | Section 7.5.40 |
0x2B | VBAT_LSB | SAR ADC Conversion 1 | Section 7.5.41 |
0x2C | TEMP | SAR ADC Conversion 2 | Section 7.5.42 |
0x30 | INT & CLK CFG | Section 7.5.43 | |
0x31 | DIN_PD | Digital Input Pin Pull Down | Section 7.5.44 |
0x32 | MISC | Misc Configuration | Section 7.5.45 |
0x33 | BOOST_CFG1 | Boost Configure 1 | Section 7.5.46 |
0x34 | BOOST_CFG2 | Boost Configure 2 | Section 7.5.47 |
0x35 | BOOST_CFG3 | Boost Configure 3 | Section 7.5.48 |
0x3B | MISC | Section 7.5.49 | |
0x3F | TG_CFG0 | Tone Generator | Section 7.5.50 |
0x40 | BST_ILIM_CFG0 | Boost ILIM configuration-0 | Section 7.5.51 |
0x41 | PDM_CONFIG0 | Section 7.5.52 | |
0x42 | DIN_PD & PDM_CONFIG3 | Section 7.5.53 | |
0x43 | ASI2_CONFIG0 | Section 7.5.54 | |
0x44 | ASI2_CONFIG1 | Section 7.5.55 | |
0x45 | ASI2_CONFIG2 | Section 7.5.56 | |
0x46 | ASI2_CONFIG3 | Section 7.5.57 | |
0x49 | PVDD_MSB_DSP | SAR ADC Conversion 0 | Section 7.5.58 |
0x4A | PVDD_LSB_DSP | SAR ADC Conversion 1 | Section 7.5.59 |
0x7D | REV_ID | Revision and PG ID | Section 7.5.60 |
0x7E | I2C_CKSUM | I2C Checksum | Section 7.5.61 |
0x7F | BOOK | Device Book | Section 7.5.62 |