SLOS918A August   2015  – October 2015 TAS5404-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements for I2C Interface Signals
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Descption
      1. 9.3.1  Preamplifier
      2. 9.3.2  Pulse-Width Modulator (PWM)
      3. 9.3.3  Gate Drive
      4. 9.3.4  Power FETs
      5. 9.3.5  Load Diagnostics
      6. 9.3.6  Protection and Monitoring
      7. 9.3.7  I2C Serial Communication Bus
      8. 9.3.8  I2C Bus Protocol
      9. 9.3.9  Hardware Control Pins
      10. 9.3.10 AM Radio Avoidance
    4. 9.4 Device Functional Modes
      1. 9.4.1 Audio Shutdown and Restart Sequence
      2. 9.4.2 Latched-Fault Shutdown and Restart Sequence Control
    5. 9.5 Programming
      1. 9.5.1 Random Write
      2. 9.5.2 Sequential Write
      3. 9.5.3 Random Read
      4. 9.5.4 Sequential Read
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Hardware and Software Design
        2. Parallel Operation (PBTL)
        3. Input Filter Design
        4. Amplifier Output Filtering
        5. Line Driver Applications
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
    4. 12.4 Electrical Connection of Heat Slug and Heat Sink
    5. 12.5 EMI Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

  • The EVM layout optimizes for low noise and EMC performance.
  • The TAS5404-Q1 device has a thermal pad up, so a the layout must take into account an external heatsink.
  • Layout also affects EMC performance.
  • The EVM PCB illustrations form the basis for the layout discussions.

12.2 Layout Example

The areas in Figure 23 and Figure 24 indicated by the label "A", are critical to proper operation and EMC layout. The PVDD and ground-decoupling capacitors should be close to the TAS5404-Q1 device. These ground-decoupling capacitors must be on both groups of PVDD pins to ground. The ground connections of the snubber circuits must also be close to the grounds of the TAS5404-Q1 device.

TAS5404-Q1 DC_3D_top with text.png Figure 23. TAS5404 Board Layout - Top View
TAS5404-Q1 DC_3D_bottom_with_text.png Figure 24. TAS5404 Board Layout - Bottom View

Each layer in the EVM contains a ground plane. All the ground planes should be connected together through many vias to reduce the impedance between the ground layers, which provides for low inductance paths for reduced EMI.

TAS5404-Q1 DC_top_layer-gray_with_text.png Figure 25. TAS5404 Board Layout - Bottom Layer

12.3 Thermal Consideration

The design of the thermally augmented package is to interface directly to heat sinks using a thermal interface compound (for example, Arctic Silver®, Ceramique thermal compound). The heat sink then absorbs heat from the ICs and couples it to the local air. With proper thermal management the process can reach equilibrium at a lower temperature, and heat can be continually removed from the ICs. Because of the efficiency of the TAS5404-Q1 device, heat sinks can be smaller than those required for linear amplifiers of equivalent performance.

RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the following components:

  • RθJC (the thermal resistance from junction to case, or in this case the heat slug)
  • Thermal resistance of the thermal grease
  • Thermal resistance of the heat sink

One can calculate the thermal resistance of the thermal grease from the exposed heat slug area and the manufacturer's value for the area thermal resistance of the thermal grease (expressed in °C-in2/W or °C-mm2/W). The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W (4.52°C-mm2/W). The approximate exposed heat slug size for a 64-pin QFP is 0.099 in2 (64 mm2)

Dividing the example area thermal resistance of the thermal grease by the area of the heat slug gives the actual resistance through the thermal grease for both parts, which is 0.07°C/W.

The thermal resistance of thermal pads is generally considerably higher than a thin thermal-grease layer. Thermal tape has an even higher thermal resistance and should not be used at all. The heat-sink vendor generally predicts heat sink thermal resistance, either modeled using a continuous-flow dynamics (CFD) model, or measured.

Therefore, for a single monaural channel in the IC, the system RθJA = RθJC + thermal-grease resistance + heat-sink resistance.

Table 25 indicates modeled parameters for one TAS5404-Q1 device on a heat sink. The exposed pad dimensions are 8 mm × 8 mm. The junction temperature setting is at 115°C while delivering 20 watts per channel into 4-Ω loads with no clipping. The assumed thickness of the thermal grease is about 0.001 inches (0.0254 mm).

Table 25. QFP Package Modeled Parameters

Ambient temperature 25 °C
Power to load 20 W × 4
Power dissipation 1.9 W × 4
ΔT inside package 7.6 °C
ΔT through thermal grease 0.46 °C
Required heatsink thermal resistance 10.78 °C/W
Junction temperature 115 °C
System RθJA 11.85 °C/W
RθJA × power dissipation 90 °C

12.4 Electrical Connection of Heat Slug and Heat Sink

Electrically connect the heat sink attached to the heat slug of the TAS5404-Q1 device to GND, or leave it floating. Do not connect the heat slug to any other electrical node.

12.5 EMI Considerations

Automotive-level EMI performance depends on both careful integrated circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design.

The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces the EMI that results from current passing from the die to the system PCB. Each channel also operates at a different phase. The phase between channels is I2C selectable to either 45° or 180°, to reduce EMI caused by high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI.