SLOS918A August   2015  – October 2015 TAS5404-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements for I2C Interface Signals
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Descption
      1. 9.3.1  Preamplifier
      2. 9.3.2  Pulse-Width Modulator (PWM)
      3. 9.3.3  Gate Drive
      4. 9.3.4  Power FETs
      5. 9.3.5  Load Diagnostics
      6. 9.3.6  Protection and Monitoring
      7. 9.3.7  I2C Serial Communication Bus
      8. 9.3.8  I2C Bus Protocol
      9. 9.3.9  Hardware Control Pins
      10. 9.3.10 AM Radio Avoidance
    4. 9.4 Device Functional Modes
      1. 9.4.1 Audio Shutdown and Restart Sequence
      2. 9.4.2 Latched-Fault Shutdown and Restart Sequence Control
    5. 9.5 Programming
      1. 9.5.1 Random Write
      2. 9.5.2 Sequential Write
      3. 9.5.3 Random Read
      4. 9.5.4 Sequential Read
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Hardware and Software Design
        2. 10.2.2.2 Parallel Operation (PBTL)
        3. 10.2.2.3 Input Filter Design
        4. 10.2.2.4 Amplifier Output Filtering
        5. 10.2.2.5 Line Driver Applications
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
    4. 12.4 Electrical Connection of Heat Slug and Heat Sink
    5. 12.5 EMI Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Package
64-Pin QFP
(Top View)
TAS5404-Q1 pinout_phd64_5414_los673_r1.png

Pin Functions

NAME PIN TYPE(1) DESCRIPTION
A_BYP 11 PBY Bypass pin for the AVDD analog regulator
CLIP_OTW 6 DO Reports CLIP, OTW, or both. Also reports tweeter detection during tweeter mode. Open-drain
CP 41 CP Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT 40 CP Bottom of flying capacitor for charge pump
CPC_TOP 42 CP Top of flying capacitor for charge pump
D_BYP 5 PBY Bypass pin for DVDD regulator output
FAULT 1 DO Global fault output (open drain): UV, OV, OTSD, OCSD, DC
GND 3, 7, 8, 9, 12, 14, 16, 17, 21, 22, 23, 24, 25, 26, 30, 31, 32, 35, 38, 39, 43, 46, 49, 50, 51, 55, 56, 57, 58, 59, 60 GND Ground
I2C_ADDR 62 AI I2C address bit
IN1_P 13 AI Non-inverting analog input for channel 1
IN2_P 15 AI Non-inverting analog input for channel 2
IN3_P 19 AI Non-inverting analog input for channel 3
IN4_P 20 AI Non-inverting analog input for channel 4
IN_M 18 ARTN Signal return for the four analog channel inputs
MUTE 2 AI Gain ramp control: mute (low), play (high)
OSC_SYNC 61 DI/DO Oscillator input from master or output to slave amplifiers
OUT1_M 48 PO – polarity output for bridge 1
OUT1_P 47 PO + polarity output for bridge 1
OUT2_M 45 PO – polarity output for bridge 2
OUT2_P 44 PO + polarity output for bridge 2
OUT3_M 37 PO – polarity output for bridge 3
OUT3_P 36 PO + polarity output for bridge 3
OUT4_M 34 PO – polarity output for bridge 4
OUT4_P 33 PO + polarity output for bridge 4
PVDD 27, 28, 29, 52, 53, 54 PWR PVDD supply
REXT 10 AI Precision resistor pin to set analog reference
SCL 64 DI I2C clock input from system I2C master
SDA 63 DI/DO I2C data I/O for communication with system I2C master
STANDBY 4 DI Active-low STANDBY pin. Standby (low), power up (high)
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PBY = power bypass, PO = power output, GND = ground, CP = charge pump.