SLASEH5D May   2018  – November 2020 TAS5805M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Mode
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with BD Mode
      3. 6.7.3 Bridge Tied Load (BTL) Configuration Curves with Ferrite Bead + Capacitor as the Output Filter
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration with 1SPW Modulation
      5. 6.7.5 Parallel Bridge Tied Load (PBTL) Configuration with BD Modulation
  8. 7 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
        2. 7.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Spread Spectrum
        2. 7.4.3.2 Channel to Channel Phase Shift
        3. 7.4.3.3 Multi-Devices PWM Phase Synchronization
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ Coefficients Update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Device Over Voltage/Under Voltage Protection
            1. 7.5.3.3.4.1 Over Voltage Protection
            2. 7.5.3.3.4.2 Under Voltage Protection
          5. 7.5.3.3.5 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bootstrap Capacitors
      2. 8.1.2 Inductor Selections
      3. 8.1.3 Power Supply Decoupling
      4. 8.1.4 Output EMI Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedures
          1. 8.2.1.2.1 Step 1: Hardware Integration
          2. 8.2.1.2.2 Step 2: Speaker Tuning
          3. 8.2.1.2.3 Step 3: Software Integration
        3. 8.2.1.3 Application Curves
          1. 8.2.1.3.1 Audio Performance
          2. 8.2.1.3.2 EN55022 Conducted Emissions Results with Ferrite Bead as output filter
          3. 8.2.1.3.3 EN55022 Radiated Emissions Results with Ferrite Bead as output filter
      2. 8.2.2 MONO (PBTL) Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Advanced 2.1 System (Two TAS5805M Devices)
  11. 9 Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  12. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Guidelines for Audio Amplifiers
      2. 9.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 9.1.3 Optimizing Thermal Performance
        1. 9.1.3.1 Device, Copper, and Component Layout
        2. 9.1.3.2 Stencil Pattern
          1. 9.1.3.2.1 PCB footprint and Via Arrangement
          2. 9.1.3.2.2 Solder Stencil
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  14. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.1 Design Requirements

  • Power supplies:
    • 3.3-V or 1.8-V supply
    • 4.5-V to 24-V supply
  • Communication: host processor serving as I2C compliant master
  • External memory (Such as EEPROM and FLASH) used for coefficients

The requirement for the supporting components for the TAS5805M device in a Stereo 2.0 (BTL) system is provide in Table 8-3 and Table 8-4

Table 8-3 Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as output filter)
REFERENCE DESIGNATORVALUESIZEDETAILED DESCRIPTION
C1,C2,C5,C622uF0805CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
C3,C40.1uF0402CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
C74.7uF0603CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
C80.1uF0603CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
C9,C101uF0603CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
R14.70k0402RES, 4.70 k, 1%, 0.0625 W, 0402
R210.0k0404RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C140.22uF0603CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
C15,C16,C17,C18,C19,C20,C21,C22,C232200pF0603CAP, CERM, 2200 pF, 100 V,+/- 10%, X7R, 0603
R3,R4,R5,R668 ohm0603ES, 68, 5%, 0.1 W, 0603
L1,L2,L3,L4300 ohm0806Ferrite Bead, 300 ohm @ 100 MHz, 3.1 A, 0806
L5100 ohm0806Ferrite Bead, 100 ohm @ 100 MHz, 4 A, 0806

With Low EMI technology, TAS5805M keeps enough EMI margin for most of application cases where PVDD < 14V with ferrite bead (Low BOM cost). With Ferrite Bead and capacitor as the output filter, Figure 8-1 and Table 8-3 includes a good configuration (Proper value of Ferrite bead, Capacitor, Resistor) to achieve enough EMI margin for the typical case which PVDD = 12V, Speaker Load = 8Ω/6Ω, each speaker wire with 1m length, Output Power = 1W/4W/8W for each channel.

  • Select Ferrite bead (L1~L5). The trade-off is impedance and rated current. If the rated current meet the system's requirement, larger impedance means larger EMI margin for the EMI, especially for the frequency band 5 MHz~50 MHz. The typical ferrite bead recommend for TAS5805M is NFZ2MSM series (Murata) and UPZ2012E series (Sunlord). 300 ohm at 100 MHz ferrite bead is a typical value which can pass EMI for most of application cases.
  • Select capacitor (C15~C23). The trade-off is capacitor value and idle current. Larger capacitor means larger idle current, increase the capacitor value from 1nF to 2.2nF makes much help for frequency band 5 MHz~100 MHz.
  • Using Ferrite bead as the output filter, recommend designer to use Fsw = 384 kHz with Spread spectrum enable, BD Modulation, refer to Section 7.4.3.1
  • With Ferrite bead as the output power. In order to pass EMI (AC Conducted Emission) standard, an AC to DC adapter with EMI filter in it is needed. For most of applications (TV/Voice Control Speaker/Wireless speaker/Soundbar) which need a 110 V~220 V power supply usually has a EMI filter in the AC to DC adapter. Some cases use DC power supply and also need to test the DC Conducted Emission , this applications (Automotive/Industry) need a simple EMI filter on PVDD for TAS5805M. Refer to application note: AN-2162 Simple Success With Conducted EMI From DC to DC Converters.
Table 8-4 Supporting Component Requirements for Stereo 2.0 (BTL) system (With Inductor as output filter)
REFERENCE DESIGNATORVALUESIZEDETAILED DESCRIPTION
C1,C6390 µF10mmx10mmCAP, AL, 390 µF, 35 V, ±20%, 0.08 ohm, SMD
C2,C522 µF0603CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
C3,C40.1 µF0402CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
C74.7 µF0603CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
C80.1 µF0603CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
C9,C101 µF0603CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
R14.70 k0402RES, 4.70 k, 1%, 0.0625 W, 0402
R210.0 k0404RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C140.22 µF0603CAP, CERM, 0.22 µF, 50 V, ±10%, X7R, 0603
C15,C16,C17,C180.68 µF0805CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
L1,L2,L3,L410 µHInductor, Shielded, 10 µH, 4.4 A, 0.023 ohm, SMD

With Inductor as the output filter, designers can achieve ultra low idle current (with Hybrid Modulation or 1SPW Modulation) and keep large EMI margin. As the switching frequency of TAS5805M can be adjustable from 384 kHz to 768 kHz. Higher switching frequency means smaller Inductor value needed.

  • With 768 kHz switching frequency. Designers can select 10uH + 0.68 µF or 4.7 µH +0.68 µF as the output filter, this will help customer to save the Inductor size with the same rated current during the inductor selection. With 4.7uH + 0.68uF, make sure PVDD ≤ 12V to avoid the large ripple current to trigger the OC threshold (5A).
  • With 384 kHZ switching frequency. Designers can select 22 µH + 0.68 µF or 15 µH + 0.68 µF or 10 µH + 0.68 µF as the output filter, this will help customer to save power dissipation for some battery power supply application. With 10 µH + 0.68 µF, make sure PVDD ≤ 12 V to avoid the large ripple current to trigger the OC threshold (5 A).