SLOSEA8 December   2024 TAS5815

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  8. 6 Typical Characteristics
    1. 6.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
    2. 6.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
    3. 6.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
    4. 6.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Serial Audio Port - Data Formats and Bit Depths
      5. 7.3.5 Clock Halt Auto-recovery
      6. 7.3.6 Sample Rate on the Fly Change
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Minimize EMI with Spread Spectrum
        2. 7.4.3.2 Minimize EMI with channel to channel phase shift
        3. 7.4.3.3 Minimize EMI with Multi-Devices PWM Phase Synchronization
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
      7. 7.4.7 Load Detect
        1. 7.4.7.1 Short Load Detect
        2. 7.4.7.2 Open Load Detect
    5. 7.5 Programming and Control
      1. 7.5.1 I2C Serial Communication Bus
      2. 7.5.2 Target Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Random Read
        3. 7.5.2.3 Sequential Write
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 7.5.3.3.2 DC Detect
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
  10. 8 Register Maps
    1. 8.1 CONTROL PORT Registers
  11. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Bootstrap Capacitors
      2. 9.1.2 Inductor Selections
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Application
      1. 9.2.1 2.0 (Stereo BTL) System
        1. 9.2.1.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step 1: Hardware Integration
        2. 9.2.2.2 Step 2: Speaker Tuning
        3. 9.2.2.3 Step 3: Software Integration
      3. 9.2.3 MONO (PBTL) System
        1. 9.2.3.1 Design Requirements
      4. 9.2.4 Advanced 2.1 System (Two TAS5815 Devices)
  12. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  13. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  14. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  15. 13Revision History
  16. 14Mechanical and Packaging Information
    1. 14.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Free-air room temperature 25°C, 1SPW Mode, LC filter=4.7uH+0.68uF, Fsw=768kHz, Class D Bandwidth=175kHz, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital I/O
|IIH| Input logic high current level
for DVDD referenced digital
input pins		 VIN(DigIn) = VDVDD 10 uA
|IIL| Input logic low current level
for DVDD referenced digital
input pins		 VIN(DigIn) = 0 V –10 uA
VIH(Digin) Input logic high threshold for
DVDD referenced digital
inputs		 70% VDVDD
VIL(Digin) Input logic low threshold for
DVDD referenced digital
inputs		 30% VDVDD
VOH(Digin) Output logic high voltage
level		 IOH = 4 mA 80% VDVDD
VOL(Digin) Output logic low voltage level IOH = –4 mA 20% VDVDD
I2C CONTROL PORT
CL(I2C) Allowable load capacitance
for each I2C Line		 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
SERIAL AUDIO PORT
tDLY Required LRCLK/FS to SCLK
rising edge delay		 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 32 96 kHz
fSCLK Supported SCLK frequencies 32 64 fS
fSCLK SCLK frequency 24.576 MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
toff Turn-off Time Excluding volume ramp 10 ms
AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)		 29.4 dBV
ΔAV(SPK_AMP) Amplifier gain error Gain = 26.4 dBV 0.5 dB
fSPK_AMP Switching frequency of the
speaker amplifier		 384 kHz
fSPK_AMP Switching frequency of the
speaker amplifier		 768 kHz
RDS(on) Drain-to-source on resistance
of the individual output
MOSFETs		 FET + Metallization. VPVDD=24 V, I(OUT)=500 mA,
TJ=25 ℃		 120 mΩ
PROTECTION
OCETHRES Over-Current Error Threshold OUTxx Overcurrent Error Threshold 6 7 A
UVETHRES(PVDD) PVDD under voltage error
threshold condition		 3.7 4 4.2 V
OVETHRES(PVDD) PVDD over voltage error
threshold		 27 28.1 29.2 V
DCETHRES Output DC Error protection
threshold		 Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection		 1.9 V
TDCDET Output DC Detect time Class D Amplifier's output remain at or above
DCETHRES		 570 ms
OTETHRES Over temperature error
threshold		 160 ℃
OTEHystersis Over temperature error
hysteresis		 10 ℃
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit3 135 °C
OL Open Load Detection Open Load Detection for ChA or ChB or both  40 70 Ω
SL Short Load Detection Short Load Detection for ChA or ChB or both (PVDD = 13.5 V) 1 Ω
SL Short Load Detection Short Load Detection for ChA or ChB or both (PVDD = 18 V) 2 Ω
SL Short Load Detection Short Load Detection for ChA or ChB or both (PVDD = 21 V) 3 Ω
SL Short Load Detection Short Load Detection for ChA or ChB or both (PVDD = 24 V) 4 Ω
AUDIO PERFORMACNE (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4dBV
analog gain, VPVDD =
13.5 V		 –6.5 6.5 mV
PO(SPK) Output Power (Per Channel) VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
10%		 16 W
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
1%		 13 W
VPVDD = 21 V, RSPK = 4 Ω, f = 1 kHz, THD+N =
10%		 50 W
VPVDD = 21 V, RSPK = 4 Ω, f = 1 kHz, THD+N =
1%		 42 W
VPVDD = 24 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
1%		 39 W
PO(SPK) Output Power (Per Channel) VPVDD = 24 V, RSPK = 6 Ω, f = 1 kHz, THD+N =
10%		 48 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz, RSPK =
6 Ω)		 VPVDD = 18 V 0.03 %
VPVDD = 21 V 0.03 %
VPVDD = 24 V 0.03 %
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz, RSPK =
4 Ω)		 VPVDD = 21 V 0.03 %
ICN(SPK) Idle channel noise(Aweighted,
AES17)		 VPVDD = 13.5 V, LC-filter, Load=6 Ω 40 µVrms
VPVDD = 24 V, LC-filter ,Load=6 Ω 50 µVrms
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24 V		 111 dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=13.5 V		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 kHz, 1 Vrms, VPVDD = 13.5 V,
input audio signal = digital zero		 72 dB
X-talkSPK Cross-talk (worst case
between left-to-right and
right-to-left coupling)		 f = 1 kHz, based on Inductor (DFEG7030D-4R7)
from Murata		 100 dB
AUDIO PERFORMANCE (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4 dBV
Analog gain, VPVDD = 18 V		 –6.5 6.5 mV
PO(SPK) Output Power VPVDD = 24 V, RSPK = 3 Ω, f = 1 kHz, THD+N =
1%		 79 W
VPVDD = 24 V, RSPK = 3 Ω, f = 1 kHz, THD+N =
10%		 96 W
VPVDD = 18 V, RSPK = 2 Ω, f = 1 kHz, THD+N =
1%		 58 W
PO(SPK) Output Power VPVDD = 18 V, RSPK = 2 Ω, f = 1 kHz, THD+N =
10%		 75 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz)		 VPVDD = 18 V, LC-filter, RSPK = 2 Ω 0.08 %
VPVDD = 24 V, LC-filter, RSPK = 3 Ω 0.03 %
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24 V, RSPK = 4 Ω		 108 dB
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD=13.5 V, RSPK = 3 Ω		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 kHz, 1 Vrms,VPVDD = 18 V,
input audio signal = digital zero		 72 dB