SNAS648C October 2014 – February 2023 TDC1000
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| TRANSMITTER SIGNAL PATH (TX) | |||||||
| VOUT(TX) | Output voltage swing | ƒout = 1 MHz, RL = 75 Ω to VCM | HIGH | VDD – 0.32 | V | ||
| LOW | 0.32 | V | |||||
| IOUT(TX) | Output drive current | ƒout = 1 MHz, RL = 75 Ω to VCM | 22 | mARMS | |||
| ƒOUT(TX) | Output TX frequency | ƒCLKIN = 8 MHz, divide-by-2 (programmable; see GUID-CA8C83E2-9C78-4A74-B4F4-8B498F851ABD.html#TITLE-SNAS648SNAS6482450) | 4 | MHz | |||
| RECEIVER SIGNAL PATH (RX) | |||||||
| ΔtSTOP | STOP cycle-to-cycle jitter | LNA capacitive feedback, GPGA = 6 dB, ƒIN = 1 MHz, VIN = 100 mVPP, CVCOM = 1 µF and GUID-72D520D8-3AB2-4ABC-B20F-282E41D31FC0.html#SNAS6485768 | 50 | psRMS | |||
| LNA | |||||||
| GLNA | LNA gain | Capacitive feedback, CIN = 300 pF, ƒIN = 1 MHz, RL = 100 kΩ to VCM, CVCOM = 1 µF | 20 | dB | |||
| enLNA | LNA input referred noise density | Capacitive feedback, CIN = 300 pF, ƒ = 1 MHz, VDD = 3.1 V, VIN = VCM, RL = ∞, CVCOM = 1 µF | 2 | nV/√Hz | |||
| VIN(LNA) | Input voltage range | Resistive feedback, RL = 1 kΩ to VCM, CVCOM = 1 µF | HIGH | VCM + (VCM – 0.24) / (GLNA) | V | ||
| LOW | VCM – (VCM – 0.24) / (GLNA) | V | |||||
| VOUT(LNA) | Output voltage range | Resistive feedback, RL = 1 kΩ to VCM, CVCOM = 1 µF | HIGH | VDD – 0.24 | V | ||
| LOW | GND + 0.24 | V | |||||
| SRLNA | Slew rate#SNAS6485249 | Resistive feedback, RL = 1 kΩ to VCM, 100mV step, CVCOM = 1 µF | 9 | V/μs | |||
| XTK | MUX ch-to-ch crosstalk | Capacitive feedback, ƒ = 1 MHz, RL = 100 kΩ to VCM, CVCOM = 1 µF | –57 | dB | |||
| BWLNA | –3-dB bandwidth | Capacitive feedback, CIN = 300 pF, RL= 100 kΩ to VCM, CVCOM = 1 µF | 5 | MHz | |||
| VOS(LNA) | LNA input offset voltage | Resistive mode, VIN = VCM, RL = ∞ | ±320 | µV | |||
| VCOM | |||||||
| VCOM | VCOM output voltage | CVCOM = 1 µF | VCM | V | |||
| VCOM output error | 0.5% | ||||||
| PGA | |||||||
| VIN(PGA) | PGA input range | RL = 100 kΩ to VCM, CL = 10 pF to GND | HIGH | VCM + (VCM – 0.06) / (GPGA) | V | ||
| LOW | VCM – (VCM – 0.06) / (GPGA) | V | |||||
| GPGAMIN | PGA min gain | DC, RL = ∞, CL = 10 pF | 0 | dB | |||
| GPGAMAX | PGA max gain | 21 | dB | ||||
| ΔGPGA | PGA gain step size | 3 | dB | ||||
| GE(PGA) | PGA gain error | DC, GPGA = 0 dB, RL = ∞, CL = 10 pF | 5% | ||||
| TCGPGA | PGA gain temperature coefficient | DC, GPGA = 0 dB, RL = ∞, CL = 10 pF | 170 | ppm/°C | |||
| enPGA | PGA input referred noise density | GPGA = 21 dB, ƒ = 1 MHz, VDD = 3.1V, VIN = VCM, RL = ∞, CVCOM = 1 µF | 3.1 | nV/√Hz | |||
| VOUT(PGA) | Output range | RL = 100 kΩ to VCM, CL = 10 pF to GND | HIGH | VDD – 0.06 | V | ||
| LOW | 60 | mV | |||||
| BWPGA | –3-db bandwidth | GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10 pF, CVCOM = 1 µF | 5 | MHz | |||
| SRPGA | Slew rate#SNAS6485249 | GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10 pF, CVCOM = 1 µF | 12.5 | V/µs | |||
| ZERO CROSS COMPARATOR | |||||||
| VOS(COMP) | Input offset voltage#SNAS6487393 | Referred to VCOM | ±115 | µV | |||
| enCOMP | Zero crossing comparator input referred noise#SNAS6487393 | 1 MHz | 5 | nV/√Hz | |||
| HYSTCOMP | Hysteresis #SNAS6487393 | Referred to VCOM | -10 | mV | |||
| THRESHOLD DETECTOR | |||||||
| VTHDET | Threshold level | ECHO_QUAL_THLD = 0h, VCOM referred | –35 | mV | |||
| ECHO_QUAL_THLD = 7h, VCOM referred | –1.5 | V | |||||
| TEMPERATURE SENSOR INTERFACE#SNAS6488572 | |||||||
| TERROR | Temperature measurement accuracy | RREF = 1 kΩ, PT1000 range: –40 to 125°C#SNAS6484309 | 1 | °C | |||
| RREF = 1 kΩ, PT1000 range: –15°C to 85°C#SNAS6484309 | 0.5 | °C | |||||
| Relative accuracy | RREF = 1 kΩ, RRTD1 = RRTD2 = 1.1 kΩ | 0.02 | °CRMS | ||||
| TGE | Gain error | 5.8 | m°C/°C | ||||
| POWER SUPPLY | |||||||
| IDD | VDD supply current | Sleep (EN = CLKIN = TRIGGER = low) | 0.61 | µA | |||
| Continuous receive mode, LNA and PGA bypassed | 2.8 | 3 | mA | ||||
| Continuous receive mode, LNA and PGA active | 6.2 | 7.5 | mA | ||||
| Temp. measurement only (PT1000 mode)#SNAS6489855 | 370 | 400 | µA | ||||
| Temp. measurement (PT500 mode)#SNAS6486279 | 500 | 540 | µA | ||||
| IIO | VIO supply sleep current#SNAS6487393 | Sleep (EN = CLKIN = TRIGGER = low) | 2 | nA | |||
| DIGITAL INPUT/OUTPUT CHARACTERISTICS | |||||||
| VIL | Input logic low threshold | 0.2 × VIO | V | ||||
| VIH | Input logic high threshold | 0.8 × VIO | V | ||||
| VOL | Output logic low threshold | SDO pin, 100-μA current | 0.2 | V | |||
| SDO pin, 1.85-mA current | 0.4 | V | |||||
| START and STOP pins, 100-μA current | 0.5 | V | |||||
| START and STOP pins, 1.85-mA current | 0.6 | V | |||||
| ERRB pin, 100-μA current | 0.2 | V | |||||
| ERRB pin, 1.85-mA current | 0.4 | V | |||||
| VOH | Output logic high threshold | SDO pin, 100-μA current | VIO – 0.2 | V | |||
| SDO pin, 1.85-mA current | VIO – 0.6 | V | |||||
| START and STOP pins, 100-μA current | VIO – 0.5 | V | |||||
| START and STOP pins, 1.85-mA current | VIO – 0.6 | V | |||||
| ERRB pin, 0-µA current | VIO – 0.2 | V | |||||
| IOMAX | Maximum output current for SDO, START and STOP | 1.85 | mA | ||||