SLLSG10A November   2024  – February 2025 TDP142-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 DP Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC Characteristics
CPLF-LINRL0 Low-frequency –1dB compression point at LINR_L0 setting.  At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 750 mVppd
CPHF-LINRL0 High-frequency –1dB compression point at LINR_L0 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 675 mVppd
CPLF-LINRL1 Low-frequency –1dB compression point at LINR_L1 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 850 mVppd
CPHF-LINRL1 High-frequency –1dB compression point at LINR_L1 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 740 mVppd
CPLF-LINRL2 Low-frequency –1dB compression point at LINR_L2 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 975 mVppd
CPHF-LINRL2 High-frequency –1dB compression point at LINR_L2 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 800 mVppd
CPLF-LINRL3 Low-frequency –1dB compression point at LINR_L3 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 1050 mVppd
CPHF-LINRL3 High-frequency –1dB compression point at LINR_L3 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 775 mVppd
tTX_DJ TX output deterministic residual jitter VID = 0.8Vppd; Optimual EQ setting; 12in prechannel (SDD21 = –8.2dB at 5GHz); 1.6in post channel (SDD21 = –1.8dB at 5GHz); PRBS7; DP at 8.1Gbps 0.06 UI
DisplayPort Receiver
VID(PP) Peak-to-peak input differential dynamic voltage range 1400 V
VIC Input common-mode voltage 0.8 1.75 2 V
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change under following operating states:  OFF to ON, Disabled to 4DP low power, 4DP active to Disabled. (1)  Measured single-ended at non-redriver side of AC-coupling capacitor with 200kΩ load. –1200 1000 mV
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change under following operating states:  Disabled to 4DP active (D0), D0 to D3, D3 to D0. Measured single-ended at non-redriver side of AC-coupling capacitor with  50Ω load. –500 1000 mV
dR Data rate 8.1 Gbps
R(ti) Input termination resistance 72 90 110 Ω
C(AC) External required AC-coupling capacitor 75 265 nF
EQ_DP0 DP0 Receiver equalization at 100MHz DP0EQ_SEL = 0; –0.2 dB
EQ_DP15 DP0 Receiver equalization at 100MHz DP0EQ_SEL = 15; 2.3 dB
EQ_DP0 DP0 Receiver equalization at 4.05GHz DP0EQ_SEL = 0; 0.6 dB
EQ_DP15 DP0 Receiver equalization at 4.05GHz DP0EQ_SEL = 15; 14.5 dB
DisplayPort Transmitter
VTX-CM-INST Maximum instantaneous TX DC common-mode voltage change for following operating states: Disabled to 4DP active (D0), D0 to D3, D3 to D0. Measured at non-redriver side of AC-coupling capacitor with 50Ω load. –500 1000 mV
VTX-CM-INST Maximum instantaneous TX DC common-mode voltage change under following operating states: Disabled to 4DP low power, 4DP active to Disabled Measured at non-redriver side of AC-coupling capacitor with 200kΩ load. –1000 1000 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0.6 1 V
RTX(DIFF) Differential impedance of the driver 72 90 120 Ω
(1) Instantaneous common-mode excursions observed by GPU (DPTX) can be minimized by disabling redriver prior to disabling DPTX termination.