SLLSG10A November   2024  – February 2025 TDP142-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HPDIN
tHPDIN_DEBOUNCE DPEN and HPDIN debounce time when transitioning from H to L. 2 10 ms
I2C
fSCL I2C clock frequency 1 MHz
tBUF Bus-free time between START and STOP conditions Refer to Figure 6-1 0.5 µs
tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated Refer to Figure 6-1 0.26 µs
tLOW Low period of the I2C clock Refer to Figure 6-1 0.5 µs
tHIGH High period of the I2C clock Refer to Figure 6-1 0.26 µs
tSUSTA Setup time for a repeated START condition Refer to Figure 6-1 0.26 µs
tHDDAT Data hold time Refer to Figure 6-1 0.008 µs
tSUDAT Data setup time Refer to Figure 6-1 50 ns
tR Rise time of both SDA and SCL signals Refer to Figure 6-1 120 ns
tF Fall time of both SDA and SCL signals Refer to Figure 6-1 1.2 120 ns
tSUSTO Setup time for STOP condition Refer to Figure 6-1 0.26 µs
Cb Capacitive load for each bus line 150 pF