SLOS224L June   1999  – July 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - THS4031
    5. 5.5 Thermal Information - THS4032
    6. 5.6 Electrical Characteristics - RL = 150Ω
    7. 5.7 Electrical Characteristics - RL = 1kΩ
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-Pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Multiplexer Selection
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
          1. 7.2.2.3.1 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics - RL = 1kΩ

at TA = full range, VCC = ±15V, and RL = 1kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
Unity gain bandwidth VCC = ±15V, closed loop 100(1) 120 MHz
BW Small-signal bandwidth
(–3dB)		 Gain = –1V/V or 2V/V VCC = ±15V 100 MHz
VCC = ±5V 90
Bandwidth for 0.1dB flatness Gain = –1V/V or 2V/V VCC = ±15V 9 MHz
VCC = ±5V 9
Full power bandwidth(2) VCC = ±15V, VO(pp) = 20V 1.6 MHz
VCC = ±5V, VO(pp) = 5V 5.1
SR Slew rate 80(1) 100 V/μs
tS Settling time To 0.1%, gain = –1V/V VCC = ±15V, 5V step 70 ns
VCC = ±5V, 2.5V step 55
To 0.01%, gain = –1V/V VCC = ±15V, 5V step 90
VCC = ±5V, 2.5V step 80
NOISE AND DISTORTION PERFORMANCE
THD Total harmonic distortion Gain =2V/V, VCC = ±5V or ±15V,
f = 1MHz VO(pp) = 2V		 THS4031 –96 dBc
THS4032 –90
DC PERFORMANCE
Open-loop gain VCC = ±15V, VO = ±10V TA = 25°C 93 100 dB
TA = full range 92
VCC = ±5V, VO = ±2.5V TA = 25°C 92 98
TA = full range 91
VOS
Input offset voltage

 VCC = ±5V or ±15V TA = 25°C 0.3 2 mV
TA = full range 3
Offset voltage drift VCC = ±5V or ±15V, TA = full range 2 μV/°C
IIB Input bias current VCC = ±5V or ±15V TA = 25°C 9 20 μA
TA = full range 33
IOS Input offset current VCC = ±5V or ±15V TA = 25°C 30 250 nA
TA = full range 400
Input offset current drift VCC = ±5V or ±15V, TA = full range 0.2 nA/°C
INPUT CHARACTERISTICS
VICR Common-mode input voltage range VCC = ±15V ±13.5 ±14.3 V
VCC = ±5V ±3.8 ±4.3
CMRR Common-mode rejection ratio VCC = ±15V, VICR = ±12V TA = 25°C 85 95 dB
TA = full range 80
VCC = ±5V, VICR = ±2.5V TA = 25°C 90 100
TA = full range 85
Ri Input resistance 2 MΩ
Ci Input capacitance 1.5 pF
OUTPUT CHARACTERISTICS
VO Output voltage swing VCC = ±15V ±13 ±13.6 V
VCC = ±5V ±3.4 ±3.8
RO Output resistance Open loop 5 Ω
POWER SUPPLY
ICC Supply current (each amplifier) VCC = ±15V TA = 25°C 7.5 10 mA
TA = full range 11
VCC = ±5V TA = 25°C 6.5 9
TA = full range 10
PSRR Power-supply rejection ratio VCC = ±5V or ±15V TA = 25°C 85 95 dB
TA = full range 80
(1) This minimum value is not tested.
(2) Full power bandwidth = slew rate / [πVO(pp))].